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From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: intel-xe@lists.freedesktop.org, kernel-dev@igalia.com,
	"Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
	"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
	stable@vger.kernel.org
Subject: Re: [PATCH] drm/xe/xelp: Fix Wa_18022495364
Date: Mon, 19 Jan 2026 13:34:02 +0000	[thread overview]
Message-ID: <69008123-6899-49e4-9a30-b1cbff279ee4@igalia.com> (raw)
In-Reply-To: <20260116164624.GE458813@mdroper-desk1.amr.corp.intel.com>


On 16/01/2026 16:46, Matt Roper wrote:
> On Fri, Jan 16, 2026 at 09:50:40AM +0000, Tvrtko Ursulin wrote:
>> It looks I mistyped CS_DEBUG_MODE2 as CS_DEBUG_MODE1 when adding the
>> workaround. Fix it.
> 
> This matches the explanation of "option 1" for the workaround, but I'm
> wondering if we want/need this workaround at all.  Option 1 is to write
> the CS_DEBUG_MODE2 register (as you're doing here), but Option 2 is to
> do a constant cache invalidation (PIPE_CONTROL[DW1][Bit3]) during
> top-of-pipe invalidation and it looks like we already do that in general
> in emit_pipe_invalidate(), so it seems like we're implementing both
> options at the same time.  It looks like there's similar redundancy in
> i915 as well...
> 
> Are you seeing the programming of the correct register here actually
> change/fix anything?  If so, does just deleting the programming of the
> wrong register without programming the right one also fix the issue?

So far the off-line reports from people doing the testing appear to 
suggest this fix indeed, well, fixes it.

If that is confirmed we will need to add:

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13630

As to your wider conundrum - could it be that preemption is at play? 
When done from the indirect context the workaround will trigger after 
preemption, unlike when done from emit_pipe_invalidate(). So perhaps 
"Option 1" and "Option 2" you mention miss that angle?

Regards,

Tvrtko

>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
>> Fixes: ca33cd271ef9 ("drm/xe/xelp: Add Wa_18022495364")
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Cc: <stable@vger.kernel.org> # v6.18+
>> ---
>>   drivers/gpu/drm/xe/xe_lrc.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
>> index 70eae7d03a27..44f112df4eb2 100644
>> --- a/drivers/gpu/drm/xe/xe_lrc.c
>> +++ b/drivers/gpu/drm/xe/xe_lrc.c
>> @@ -1200,7 +1200,7 @@ static ssize_t setup_invalidate_state_cache_wa(struct xe_lrc *lrc,
>>   		return -ENOSPC;
>>   
>>   	*cmd++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1);
>> -	*cmd++ = CS_DEBUG_MODE1(0).addr;
>> +	*cmd++ = CS_DEBUG_MODE2(0).addr;
>>   	*cmd++ = _MASKED_BIT_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE);
>>   
>>   	return cmd - batch;
>> -- 
>> 2.52.0
>>
> 


  reply	other threads:[~2026-01-19 13:34 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-16  9:50 [PATCH] drm/xe/xelp: Fix Wa_18022495364 Tvrtko Ursulin
2026-01-16 16:46 ` Matt Roper
2026-01-19 13:34   ` Tvrtko Ursulin [this message]
2026-01-20 18:40     ` Matt Roper
  -- strict thread matches above, loose matches on Subject: below --
2026-04-20 13:16 Tvrtko Ursulin
2026-04-20 13:24 ` Tvrtko Ursulin
2026-04-20 20:29   ` Matt Roper
2026-04-21 15:09     ` Tvrtko Ursulin
2026-04-21 17:31       ` Matt Roper

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