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Wed, 8 Apr 2026 06:39:37 +0000 Message-ID: <696a1d25-bb79-4ddc-942e-196ff2e5a93c@intel.com> Date: Wed, 8 Apr 2026 09:39:33 +0300 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] mmc: sdhci-of-dwcmshc: Disable clock before DLL configuration To: Shawn Lin , Ulf Hansson CC: , , References: <1775629564-11267-1-git-send-email-shawn.lin@rock-chips.com> Content-Language: en-US From: Adrian Hunter Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki In-Reply-To: <1775629564-11267-1-git-send-email-shawn.lin@rock-chips.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: DUZPR01CA0056.eurprd01.prod.exchangelabs.com (2603:10a6:10:469::7) To IA1PR11MB7198.namprd11.prod.outlook.com (2603:10b6:208:419::15) Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA1PR11MB7198:EE_|IA1PR11MB7918:EE_ X-MS-Office365-Filtering-Correlation-Id: c0c1b403-516b-40de-486f-08de95399a82 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|366016|18002099003|56012099003|22082099003; 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In extreme cases, failing to > do so may cause the controller to malfunction completely. > > Adds a step to disable the clock before DLL configuration and > re-enables it at the end. > > Fixes: 08f3dff799d4 ("mmc: sdhci-of-dwcmshc: add rockchip platform support") > Cc: > Signed-off-by: Shawn Lin Missing colon below, otherwise: Acked-by: Adrian Hunter > --- > > Changes in v2: > - Add a comment about why passing zero to sdhci_enable_clk() > > drivers/mmc/host/sdhci-of-dwcmshc.c | 19 ++++++++++++++++--- > 1 file changed, 16 insertions(+), 3 deletions(-) > > diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c > index 6139516..5af35c9 100644 > --- a/drivers/mmc/host/sdhci-of-dwcmshc.c > +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c > @@ -783,12 +783,15 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock > extra |= BIT(4); > sdhci_writel(host, extra, reg); > > + /* Disable clock while config DLL */ > + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); > + > if (clock <= 52000000) { > if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 || > host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { > dev_err(mmc_dev(host->mmc), > "Can't reduce the clock below 52MHz in HS200/HS400 mode"); > - return; > + goto enable_clk; > } > > /* > @@ -808,7 +811,7 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock > DLL_STRBIN_DELAY_NUM_SEL | > DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET; > sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); > - return; > + goto enable_clk; > } > > /* Reset DLL */ > @@ -835,7 +838,7 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock > 500 * USEC_PER_MSEC); > if (err) { > dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n"); > - return; > + goto enable_clk; > } > > extra = 0x1 << 16 | /* tune clock stop en */ > @@ -868,6 +871,16 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock > DLL_STRBIN_TAPNUM_DEFAULT | > DLL_STRBIN_TAPNUM_FROM_SW; > sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); > + > +enable_clk Missing colon > + /* > + * The sdclk frequency select bits in SDHCI_CLOCK_CONTROL are not functional > + * on Rockchip's SDHCI implementation. Instead, the clock frequency is fully > + * controlled via external clk provider by calling clk_set_rate(). Consequently, > + * passing 0 to sdhci_enable_clk() only re-enables the already-configured clock, > + * which matches the hardware's actual behavior. > + */ > + sdhci_enable_clk(host, 0); > } > > static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask)