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X-CSE-ConnectionGUID: 2RHIMn4STWCwU+MJ2J9lkg== X-CSE-MsgGUID: EsbJc32NSh+O6K0PPhNnfA== X-IronPort-AV: E=McAfee;i="6800,10657,11720"; a="77665521" X-IronPort-AV: E=Sophos;i="6.23,103,1770624000"; d="scan'208";a="77665521" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2026 08:20:35 -0800 X-CSE-ConnectionGUID: vvFUnAmEQhqHr7+mSAu92g== X-CSE-MsgGUID: PuFsX3xER9m3MMVFQvw0FQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,103,1770624000"; d="scan'208";a="218719952" Received: from gabaabhi-mobl2.amr.corp.intel.com (HELO [10.125.109.20]) ([10.125.109.20]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2026 08:20:36 -0800 Message-ID: <7d312ba6-58a0-48cb-92fa-d8094ddef21f@intel.com> Date: Thu, 5 Mar 2026 08:20:43 -0800 Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] x86/cpu/centaur: Disable X86_FEATURE_FSGSBASE on Zhaoxin C4600 To: Tony W Wang-oc , me@ziyao.cc Cc: andrew.cooper3@citrix.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, linux-kernel@vger.kernel.org, mingo@redhat.com, stable@vger.kernel.org, tglx@kernel.org, x86@kernel.org, David Wang , lukelin@viacpu.com, brucechang@via-alliance.com, "TimGuo@zhaoxin.com" , cooperyan@zhaoxin.com, benjaminpan@viatech.com, TimGuo-oc@zhaoxin.com, QiyuanWang@zhaoxin.com, HerryYang@zhaoxin.com, "CobeChen@zhaoxin.com" References: <20260228173704.62460-1-me@ziyao.cc> <70139192-54e5-4a4b-bc96-1fe3ec4f7a0b@zhaoxin.com> From: Dave Hansen Content-Language: en-US Autocrypt: addr=dave.hansen@intel.com; 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charset=UTF-8 Content-Transfer-Encoding: 8bit On 3/5/26 01:03, Tony W Wang-oc wrote: > --- a/arch/x86/kernel/cpu/zhaoxin.c > +++ b/arch/x86/kernel/cpu/zhaoxin.c > @@ -89,6 +89,11 @@ static void init_zhaoxin(struct cpuinfo_x86 *c) >         set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); >  #endif > > +       if (c->x86 == 6 && c->x86_model == 25 && c->x86_stepping <= 3) { > +               pr_warn_once("CPU has broken FSGSBASE support; clear > FSGSBASE feature\n"); > +               setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); > +       } > + Folks, we have vendor-generic infrastructure to handle these today. You don't need to hack copied and pasted code across vendor-specific files. You just need some "VFM" defines for the models: #define Z_MODEL_HERE VFM_MAKE(X86_VENDOR_ZHAOXIN, 6, 26) #define C_MODEL_HERE VFM_MAKE(X86_VENDOR_ZHAOXIN, ...) a table: static const struct x86_cpu_id bum_fsgsbase[] __initconst = { X86_MATCH_VFM_STEPS(Z_MODEL_HERE, X86_STEP_MIN, 0x3, 1), X86_MATCH_VFM_STEPS(C_MODEL_HERE, ..., 1), }; and this code: if (x86_match_cpu(bum_fsgsbase)) setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); That code happens _once_. You can even call it from vendor-independent code. If you get fixed microcode that can also be extended to store a fixed microcode version (although we're moving away from doing this on Intel). Just please give the models some semi-sane model name.