From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BB2FC4332F for ; Tue, 13 Dec 2022 05:07:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234425AbiLMFH2 (ORCPT ); Tue, 13 Dec 2022 00:07:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49788 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234635AbiLMFHH (ORCPT ); Tue, 13 Dec 2022 00:07:07 -0500 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F0C61F9FE; Mon, 12 Dec 2022 21:04:47 -0800 (PST) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BD4JFmg009470; Tue, 13 Dec 2022 05:04:35 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=qcppdkim1; bh=S4QDHcpyU6wAfcipYSlUVNecmt6uJ+wlK9Fqca+I30A=; b=RPNmJECjldvSZw5xDNK6BZ2rEfaROceec6O3qktn8v5Vy00aD3b25MxdTK6PM5QfkElJ 7ZfpiOJo4jjDWkCcu3MbOeDm+YwQxMDxGQrHw/4ngN9mQV8RCr1BNGuVr0JH/v8uEHte FrFqBTCQRTJ0baL+2DPmuFejYI4F/jJedjCtcHpFD8ZmWxNI/7soKtyAGb7ok8vFcWpR ZlTedAA6/NmUuDEIQ/I0pZ4YDsD+t5Oaffjz8W+3mNzv4eladdPAC/Fw3FvpP1rPskVs 30xZ3syKcnj7UtzgzwVGxdu7hCa2hxEiN9S1YYjadb/5K+aTx2nROokZmyb96oXjuh8m YQ== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3megc5rfbg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 13 Dec 2022 05:04:35 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 2BD54YO0013064 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 13 Dec 2022 05:04:34 GMT Received: from [10.50.38.23] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Mon, 12 Dec 2022 21:04:29 -0800 Message-ID: <7e844687-019d-79e8-cda2-7bdee7da27ec@quicinc.com> Date: Tue, 13 Dec 2022 10:34:25 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.3.2 Subject: Re: [PATCH v2 03/13] arm64: dts: qcom: sdm845: Fix the base addresses of LLCC banks To: Manivannan Sadhasivam , , , , , CC: , , , , , , , , , References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> <20221212123311.146261-4-manivannan.sadhasivam@linaro.org> From: Sai Prakash Ranjan In-Reply-To: <20221212123311.146261-4-manivannan.sadhasivam@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 2RuYrJtLppooMZZWwsfEyHmDs3g-Am6A X-Proofpoint-GUID: 2RuYrJtLppooMZZWwsfEyHmDs3g-Am6A X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-13_01,2022-12-12_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 mlxlogscore=971 suspectscore=0 spamscore=0 priorityscore=1501 impostorscore=0 clxscore=1011 bulkscore=0 lowpriorityscore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2212130045 Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org On 12/12/2022 6:03 PM, Manivannan Sadhasivam wrote: > The LLCC block has several banks each with a different base address > and holes in between. So it is not a correct approach to cover these > banks with a single offset/size. Instead, the individual bank's base > address needs to be specified in devicetree with the exact size. > > Also, let's get rid of reg-names property as it is not needed anymore. > The driver is expected to parse the reg field based on index to get the > addresses of each LLCC banks. > > Cc: # 5.4 > Fixes: ba0411ddd133 ("arm64: dts: sdm845: Add device node for Last level cache controller") > Reported-by: Parikshit Pareek > Signed-off-by: Manivannan Sadhasivam > --- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index 65032b94b46d..683b861e060d 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -2132,8 +2132,9 @@ uart15: serial@a9c000 { > > llcc: system-cache-controller@1100000 { > compatible = "qcom,sdm845-llcc"; > - reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>; > - reg-names = "llcc_base", "llcc_broadcast_base"; > + reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>, > + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, > + <0 0x01300000 0 0x50000>; > interrupts = ; > }; > Reviewed-by: Sai Prakash Ranjan