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From:   Heiko Stuebner <heiko@sntech.de>
To:     atishp@atishpatra.org, Conor Dooley <mail@conchuod.ie>
Cc:     ajones@ventanamicro.com, anup@brainfault.org,
        conor.dooley@microchip.com, jrtc27@jrtc27.com,
        linux-riscv@lists.infradead.org, lkp@intel.com,
        mchitale@ventanamicro.com, nathan@kernel.org, palmer@rivosinc.com,
        stable@vger.kernel.org, Atish Patra <atishp@rivosinc.com>
Subject: Re: [PATCH v4] RISC-V: Clean up the Zicbom block size probing
Date:   Tue, 13 Sep 2022 09:11:45 +0200
Message-ID: <8114822.T7Z3S40VBb@phil>
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Am Dienstag, 13. September 2022, 00:48:01 CEST schrieb Conor Dooley:
> From: Palmer Dabbelt <palmer@rivosinc.com>
> 
> This fixes two issues: I truncated the warning's hart ID when porting to
> the 64-bit hart ID code, and the original code's warning handling could
> fire on an uninitialized hart ID.
> 
> The biggest change here is that riscv_cbom_block_size is no longer
> initialized, as IMO the default isn't sane: there's nothing in the ISA
> that mandates any specific cache block size, so falling back to one will
> just silently produce the wrong answer on some systems.  This also
> changes the probing order so the cache block size is known before
> enabling Zicbom support.
> 
> CC: stable@vger.kernel.org
> CC: Andrew Jones <ajones@ventanamicro.com>
> CC: Heiko Stuebner <heiko@sntech.de>
> CC: Atish Patra <atishp@rivosinc.com>
> Fixes: 3aefb2ee5bdd ("riscv: implement Zicbom-based CMO instructions + the t-head variant")
> Fixes: 1631ba1259d6 ("riscv: Add support for non-coherent devices using zicbom extension")
> Reported-by: kernel test robot <lkp@intel.com>
> Reported-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> [Conor: fixed the redefinition errors]
> Tested-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>