[PATCH v9 1/4] serial: 8250: fix panic due to PSLVERR

[PATCH v9 1/4] serial: 8250: fix panic due to PSLVERR

[Yunhui Cui]

When the PSLVERR_RESP_EN parameter is set to 1, the device generates
an error response if an attempt is made to read an empty RBR (Receive
Buffer Register) while the FIFO is enabled.

In serial8250_do_startup(), calling serial_port_out(port, UART_LCR,
UART_LCR_WLEN8) triggers dw8250_check_lcr(), which invokes
dw8250_force_idle() and serial8250_clear_and_reinit_fifos(). The latter
function enables the FIFO via serial_out(p, UART_FCR, p->fcr).
Execution proceeds to the serial_port_in(port, UART_RX).
This satisfies the PSLVERR trigger condition.

When another CPU (e.g., using printk()) is accessing the UART (UART
is busy), the current CPU fails the check (value & ~UART_LCR_SPAR) ==
(lcr & ~UART_LCR_SPAR) in dw8250_check_lcr(), causing it to enter
dw8250_force_idle().

Put serial_port_out(port, UART_LCR, UART_LCR_WLEN8) under the port->lock
to fix this issue.

Panic backtrace:
[    0.442336] Oops - unknown exception [#1]
[    0.442343] epc : dw8250_serial_in32+0x1e/0x4a
[    0.442351]  ra : serial8250_do_startup+0x2c8/0x88e
...
[    0.442416] console_on_rootfs+0x26/0x70

Fixes: c49436b657d0 ("serial: 8250_dw: Improve unwritable LCR workaround")
Link: https://lore.kernel.org/all/84cydt5peu.fsf@jogness.linutronix.de/T/
Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
Cc: stable@vger.kernel.org
---
 drivers/tty/serial/8250/8250_port.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
index 6d7b8c4667c9c..07fe818dffa34 100644
--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
@@ -2376,9 +2376,10 @@ int serial8250_do_startup(struct uart_port *port)
 	/*
 	 * Now, initialize the UART
 	 */
-	serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
 
 	uart_port_lock_irqsave(port, &flags);
+	serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
+
 	if (up->port.flags & UPF_FOURPORT) {
 		if (!up->port.irq)
 			up->port.mctrl |= TIOCM_OUT1;
-- 
2.39.5

[PATCH v9 2/4] serial: 8250_dw: fix PSLVERR on RX_TIMEOUT

[Yunhui Cui]

The DW UART may trigger the RX_TIMEOUT interrupt without data
present and remain stuck in this state indefinitely. The
dw8250_handle_irq() function detects this condition by checking
if the UART_LSR_DR bit is not set when RX_TIMEOUT occurs. When
detected, it performs a "dummy read" to recover the DW UART from
this state.

When the PSLVERR_RESP_EN parameter is set to 1, reading the UART_RX
while the FIFO is enabled and UART_LSR_DR is not set will generate a
PSLVERR error, which may lead to a system panic. There are two methods
to prevent PSLVERR: one is to check if UART_LSR_DR is set before reading
UART_RX when the FIFO is enabled, and the other is to read UART_RX when
the FIFO is disabled.

Given these two scenarios, the FIFO must be disabled before the
"dummy read" operation and re-enabled afterward to maintain normal
UART functionality.

Fixes: 424d79183af0 ("serial: 8250_dw: Avoid "too much work" from bogus rx timeout interrupt")
Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
Cc: stable@vger.kernel.org
---
 drivers/tty/serial/8250/8250_dw.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index 1902f29444a1c..082b7fcf251db 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -297,9 +297,17 @@ static int dw8250_handle_irq(struct uart_port *p)
 		uart_port_lock_irqsave(p, &flags);
 		status = serial_lsr_in(up);
 
-		if (!(status & (UART_LSR_DR | UART_LSR_BI)))
+		if (!(status & (UART_LSR_DR | UART_LSR_BI))) {
+			/* To avoid PSLVERR, disable the FIFO first. */
+			if (up->fcr & UART_FCR_ENABLE_FIFO)
+				serial_out(up, UART_FCR, 0);
+
 			serial_port_in(p, UART_RX);
 
+			if (up->fcr & UART_FCR_ENABLE_FIFO)
+				serial_out(up, UART_FCR, up->fcr);
+		}
+
 		uart_port_unlock_irqrestore(p, flags);
 	}
 
-- 
2.39.5

Re: [PATCH v9 1/4] serial: 8250: fix panic due to PSLVERR

[John Ogness]

On 2025-06-10, Yunhui Cui <cuiyunhui@bytedance.com> wrote:
> When the PSLVERR_RESP_EN parameter is set to 1, the device generates
> an error response if an attempt is made to read an empty RBR (Receive
> Buffer Register) while the FIFO is enabled.
>
> In serial8250_do_startup(), calling serial_port_out(port, UART_LCR,
> UART_LCR_WLEN8) triggers dw8250_check_lcr(), which invokes
> dw8250_force_idle() and serial8250_clear_and_reinit_fifos(). The latter
> function enables the FIFO via serial_out(p, UART_FCR, p->fcr).
> Execution proceeds to the serial_port_in(port, UART_RX).
> This satisfies the PSLVERR trigger condition.
>
> When another CPU (e.g., using printk()) is accessing the UART (UART
> is busy), the current CPU fails the check (value & ~UART_LCR_SPAR) ==
> (lcr & ~UART_LCR_SPAR) in dw8250_check_lcr(), causing it to enter
> dw8250_force_idle().
>
> Put serial_port_out(port, UART_LCR, UART_LCR_WLEN8) under the port->lock
> to fix this issue.
>
> Panic backtrace:
> [    0.442336] Oops - unknown exception [#1]
> [    0.442343] epc : dw8250_serial_in32+0x1e/0x4a
> [    0.442351]  ra : serial8250_do_startup+0x2c8/0x88e
> ...
> [    0.442416] console_on_rootfs+0x26/0x70
>
> Fixes: c49436b657d0 ("serial: 8250_dw: Improve unwritable LCR workaround")
> Link: https://lore.kernel.org/all/84cydt5peu.fsf@jogness.linutronix.de/T/
> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> Cc: stable@vger.kernel.org

Reviewed-by: John Ogness <john.ogness@linutronix.de>

Re: [PATCH v9 2/4] serial: 8250_dw: fix PSLVERR on RX_TIMEOUT

[yunhui cui]

Hi John,


On Tue, Jun 10, 2025 at 5:22 PM Yunhui Cui <cuiyunhui@bytedance.com> wrote:
>
> The DW UART may trigger the RX_TIMEOUT interrupt without data
> present and remain stuck in this state indefinitely. The
> dw8250_handle_irq() function detects this condition by checking
> if the UART_LSR_DR bit is not set when RX_TIMEOUT occurs. When
> detected, it performs a "dummy read" to recover the DW UART from
> this state.
>
> When the PSLVERR_RESP_EN parameter is set to 1, reading the UART_RX
> while the FIFO is enabled and UART_LSR_DR is not set will generate a
> PSLVERR error, which may lead to a system panic. There are two methods
> to prevent PSLVERR: one is to check if UART_LSR_DR is set before reading
> UART_RX when the FIFO is enabled, and the other is to read UART_RX when
> the FIFO is disabled.
>
> Given these two scenarios, the FIFO must be disabled before the
> "dummy read" operation and re-enabled afterward to maintain normal
> UART functionality.
>
> Fixes: 424d79183af0 ("serial: 8250_dw: Avoid "too much work" from bogus rx timeout interrupt")
> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> Cc: stable@vger.kernel.org
> ---
>  drivers/tty/serial/8250/8250_dw.c | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
> index 1902f29444a1c..082b7fcf251db 100644
> --- a/drivers/tty/serial/8250/8250_dw.c
> +++ b/drivers/tty/serial/8250/8250_dw.c
> @@ -297,9 +297,17 @@ static int dw8250_handle_irq(struct uart_port *p)
>                 uart_port_lock_irqsave(p, &flags);
>                 status = serial_lsr_in(up);
>
> -               if (!(status & (UART_LSR_DR | UART_LSR_BI)))
> +               if (!(status & (UART_LSR_DR | UART_LSR_BI))) {
> +                       /* To avoid PSLVERR, disable the FIFO first. */
> +                       if (up->fcr & UART_FCR_ENABLE_FIFO)
> +                               serial_out(up, UART_FCR, 0);
> +
>                         serial_port_in(p, UART_RX);
>
> +                       if (up->fcr & UART_FCR_ENABLE_FIFO)
> +                               serial_out(up, UART_FCR, up->fcr);
> +               }
> +
>                 uart_port_unlock_irqrestore(p, flags);
>         }
>
> --
> 2.39.5
>

Any comments on this patch?

Thanks,
Yunhui

Re: [PATCH v9 2/4] serial: 8250_dw: fix PSLVERR on RX_TIMEOUT

[John Ogness]

Hi Yunhui,

On 2025-06-23, yunhui cui <cuiyunhui@bytedance.com> wrote:
>> The DW UART may trigger the RX_TIMEOUT interrupt without data
>> present and remain stuck in this state indefinitely. The
>> dw8250_handle_irq() function detects this condition by checking
>> if the UART_LSR_DR bit is not set when RX_TIMEOUT occurs. When
>> detected, it performs a "dummy read" to recover the DW UART from
>> this state.
>>
>> When the PSLVERR_RESP_EN parameter is set to 1, reading the UART_RX
>> while the FIFO is enabled and UART_LSR_DR is not set will generate a
>> PSLVERR error, which may lead to a system panic. There are two methods
>> to prevent PSLVERR: one is to check if UART_LSR_DR is set before reading
>> UART_RX when the FIFO is enabled, and the other is to read UART_RX when
>> the FIFO is disabled.
>>
>> Given these two scenarios, the FIFO must be disabled before the
>> "dummy read" operation and re-enabled afterward to maintain normal
>> UART functionality.
>>
>> Fixes: 424d79183af0 ("serial: 8250_dw: Avoid "too much work" from bogus rx timeout interrupt")
>> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
>> Cc: stable@vger.kernel.org
>> ---
>>  drivers/tty/serial/8250/8250_dw.c | 10 +++++++++-
>>  1 file changed, 9 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
>> index 1902f29444a1c..082b7fcf251db 100644
>> --- a/drivers/tty/serial/8250/8250_dw.c
>> +++ b/drivers/tty/serial/8250/8250_dw.c
>> @@ -297,9 +297,17 @@ static int dw8250_handle_irq(struct uart_port *p)
>>                 uart_port_lock_irqsave(p, &flags);
>>                 status = serial_lsr_in(up);
>>
>> -               if (!(status & (UART_LSR_DR | UART_LSR_BI)))
>> +               if (!(status & (UART_LSR_DR | UART_LSR_BI))) {
>> +                       /* To avoid PSLVERR, disable the FIFO first. */
>> +                       if (up->fcr & UART_FCR_ENABLE_FIFO)
>> +                               serial_out(up, UART_FCR, 0);
>> +
>>                         serial_port_in(p, UART_RX);
>>
>> +                       if (up->fcr & UART_FCR_ENABLE_FIFO)
>> +                               serial_out(up, UART_FCR, up->fcr);
>> +               }
>> +
>>                 uart_port_unlock_irqrestore(p, flags);
>>         }
>>
>> --
>> 2.39.5
>
> Any comments on this patch?

I do not know enough about the hardware. Is a dummy read really the only
way to exit the RX_TIMEOUT state?

What if there are bytes in the TX-FIFO. Are they in danger of being
cleared?

From [0] I see:

"Writing a "0" to bit 0 will disable the FIFOs, in essence turning the
 UART into 8250 compatibility mode. In effect this also renders the rest
 of the settings in this register to become useless. If you write a "0"
 here it will also stop the FIFOs from sending or receiving data, so any
 data that is sent through the serial data port may be scrambled after
 this setting has been changed. It would be recommended to disable FIFOs
 only if you are trying to reset the serial communication protocol and
 clearing any working buffers you may have in your application
 software. Some documentation suggests that setting this bit to "0" also
 clears the FIFO buffers, but I would recommend explicit buffer clearing
 instead using bits 1 and 2."

Have you performed tests where you fill the TX-FIFO and then
disable/enable the FIFO to see if the TX-bytes survive?

John Ogness

[0] https://en.wikibooks.org/wiki/Serial_Programming/8250_UART_Programming

Re: [External] Re: [PATCH v9 2/4] serial: 8250_dw: fix PSLVERR on RX_TIMEOUT

[yunhui cui]

Hi John,

On Mon, Jun 23, 2025 at 4:32 PM John Ogness <john.ogness@linutronix.de> wrote:
>
> Hi Yunhui,
>
> On 2025-06-23, yunhui cui <cuiyunhui@bytedance.com> wrote:
> >> The DW UART may trigger the RX_TIMEOUT interrupt without data
> >> present and remain stuck in this state indefinitely. The
> >> dw8250_handle_irq() function detects this condition by checking
> >> if the UART_LSR_DR bit is not set when RX_TIMEOUT occurs. When
> >> detected, it performs a "dummy read" to recover the DW UART from
> >> this state.
> >>
> >> When the PSLVERR_RESP_EN parameter is set to 1, reading the UART_RX
> >> while the FIFO is enabled and UART_LSR_DR is not set will generate a
> >> PSLVERR error, which may lead to a system panic. There are two methods
> >> to prevent PSLVERR: one is to check if UART_LSR_DR is set before reading
> >> UART_RX when the FIFO is enabled, and the other is to read UART_RX when
> >> the FIFO is disabled.
> >>
> >> Given these two scenarios, the FIFO must be disabled before the
> >> "dummy read" operation and re-enabled afterward to maintain normal
> >> UART functionality.
> >>
> >> Fixes: 424d79183af0 ("serial: 8250_dw: Avoid "too much work" from bogus rx timeout interrupt")
> >> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> >> Cc: stable@vger.kernel.org
> >> ---
> >>  drivers/tty/serial/8250/8250_dw.c | 10 +++++++++-
> >>  1 file changed, 9 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
> >> index 1902f29444a1c..082b7fcf251db 100644
> >> --- a/drivers/tty/serial/8250/8250_dw.c
> >> +++ b/drivers/tty/serial/8250/8250_dw.c
> >> @@ -297,9 +297,17 @@ static int dw8250_handle_irq(struct uart_port *p)
> >>                 uart_port_lock_irqsave(p, &flags);
> >>                 status = serial_lsr_in(up);
> >>
> >> -               if (!(status & (UART_LSR_DR | UART_LSR_BI)))
> >> +               if (!(status & (UART_LSR_DR | UART_LSR_BI))) {
> >> +                       /* To avoid PSLVERR, disable the FIFO first. */
> >> +                       if (up->fcr & UART_FCR_ENABLE_FIFO)
> >> +                               serial_out(up, UART_FCR, 0);
> >> +
> >>                         serial_port_in(p, UART_RX);
> >>
> >> +                       if (up->fcr & UART_FCR_ENABLE_FIFO)
> >> +                               serial_out(up, UART_FCR, up->fcr);
> >> +               }
> >> +
> >>                 uart_port_unlock_irqrestore(p, flags);
> >>         }
> >>
> >> --
> >> 2.39.5
> >
> > Any comments on this patch?
>
> I do not know enough about the hardware. Is a dummy read really the only
> way to exit the RX_TIMEOUT state?
>
> What if there are bytes in the TX-FIFO. Are they in danger of being
> cleared?
>
> From [0] I see:
>
> "Writing a "0" to bit 0 will disable the FIFOs, in essence turning the
>  UART into 8250 compatibility mode. In effect this also renders the rest
>  of the settings in this register to become useless. If you write a "0"
>  here it will also stop the FIFOs from sending or receiving data, so any
>  data that is sent through the serial data port may be scrambled after
>  this setting has been changed. It would be recommended to disable FIFOs
>  only if you are trying to reset the serial communication protocol and
>  clearing any working buffers you may have in your application
>  software. Some documentation suggests that setting this bit to "0" also
>  clears the FIFO buffers, but I would recommend explicit buffer clearing
>  instead using bits 1 and 2."
>
> Have you performed tests where you fill the TX-FIFO and then
> disable/enable the FIFO to see if the TX-bytes survive?

Sorry, I haven't conducted relevant tests. The reason I made this
modification is that it clearly contradicts the logic of avoiding
PSLVERR. Disabling the FIFO can at least prevent the Panic() caused by
PSVERR.

>
> John Ogness
>
> [0] https://en.wikibooks.org/wiki/Serial_Programming/8250_UART_Programming

Thanks,
Yunhui

Re: [External] Re: [PATCH v9 1/4] serial: 8250: fix panic due to PSLVERR

[yunhui cui]

Hi John,

On Fri, Jun 20, 2025 at 7:20 PM John Ogness <john.ogness@linutronix.de> wrote:
>
> On 2025-06-10, Yunhui Cui <cuiyunhui@bytedance.com> wrote:
> > When the PSLVERR_RESP_EN parameter is set to 1, the device generates
> > an error response if an attempt is made to read an empty RBR (Receive
> > Buffer Register) while the FIFO is enabled.
> >
> > In serial8250_do_startup(), calling serial_port_out(port, UART_LCR,
> > UART_LCR_WLEN8) triggers dw8250_check_lcr(), which invokes
> > dw8250_force_idle() and serial8250_clear_and_reinit_fifos(). The latter
> > function enables the FIFO via serial_out(p, UART_FCR, p->fcr).
> > Execution proceeds to the serial_port_in(port, UART_RX).
> > This satisfies the PSLVERR trigger condition.
> >
> > When another CPU (e.g., using printk()) is accessing the UART (UART
> > is busy), the current CPU fails the check (value & ~UART_LCR_SPAR) ==
> > (lcr & ~UART_LCR_SPAR) in dw8250_check_lcr(), causing it to enter
> > dw8250_force_idle().
> >
> > Put serial_port_out(port, UART_LCR, UART_LCR_WLEN8) under the port->lock
> > to fix this issue.
> >
> > Panic backtrace:
> > [    0.442336] Oops - unknown exception [#1]
> > [    0.442343] epc : dw8250_serial_in32+0x1e/0x4a
> > [    0.442351]  ra : serial8250_do_startup+0x2c8/0x88e
> > ...
> > [    0.442416] console_on_rootfs+0x26/0x70
> >
> > Fixes: c49436b657d0 ("serial: 8250_dw: Improve unwritable LCR workaround")
> > Link: https://lore.kernel.org/all/84cydt5peu.fsf@jogness.linutronix.de/T/
> > Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> > Cc: stable@vger.kernel.org
>
> Reviewed-by: John Ogness <john.ogness@linutronix.de>

In this patchset, patch[4] has been dropped, and patch[2] may still
need discussion. Could you please pick patch[1] and patch[3] first?

Thanks,
Yunhui

Re: [External] Re: [PATCH v9 1/4] serial: 8250: fix panic due to PSLVERR

[Greg KH]

On Thu, Jul 17, 2025 at 08:19:48PM +0800, yunhui cui wrote:
> Hi John,
> 
> On Fri, Jun 20, 2025 at 7:20 PM John Ogness <john.ogness@linutronix.de> wrote:
> >
> > On 2025-06-10, Yunhui Cui <cuiyunhui@bytedance.com> wrote:
> > > When the PSLVERR_RESP_EN parameter is set to 1, the device generates
> > > an error response if an attempt is made to read an empty RBR (Receive
> > > Buffer Register) while the FIFO is enabled.
> > >
> > > In serial8250_do_startup(), calling serial_port_out(port, UART_LCR,
> > > UART_LCR_WLEN8) triggers dw8250_check_lcr(), which invokes
> > > dw8250_force_idle() and serial8250_clear_and_reinit_fifos(). The latter
> > > function enables the FIFO via serial_out(p, UART_FCR, p->fcr).
> > > Execution proceeds to the serial_port_in(port, UART_RX).
> > > This satisfies the PSLVERR trigger condition.
> > >
> > > When another CPU (e.g., using printk()) is accessing the UART (UART
> > > is busy), the current CPU fails the check (value & ~UART_LCR_SPAR) ==
> > > (lcr & ~UART_LCR_SPAR) in dw8250_check_lcr(), causing it to enter
> > > dw8250_force_idle().
> > >
> > > Put serial_port_out(port, UART_LCR, UART_LCR_WLEN8) under the port->lock
> > > to fix this issue.
> > >
> > > Panic backtrace:
> > > [    0.442336] Oops - unknown exception [#1]
> > > [    0.442343] epc : dw8250_serial_in32+0x1e/0x4a
> > > [    0.442351]  ra : serial8250_do_startup+0x2c8/0x88e
> > > ...
> > > [    0.442416] console_on_rootfs+0x26/0x70
> > >
> > > Fixes: c49436b657d0 ("serial: 8250_dw: Improve unwritable LCR workaround")
> > > Link: https://lore.kernel.org/all/84cydt5peu.fsf@jogness.linutronix.de/T/
> > > Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> > > Cc: stable@vger.kernel.org
> >
> > Reviewed-by: John Ogness <john.ogness@linutronix.de>
> 
> In this patchset, patch[4] has been dropped, and patch[2] may still
> need discussion. Could you please pick patch[1] and patch[3] first?

Please resend just the patches you want applied, picking out of a series
is hard with our current tools, and confusing.

thanks,

greg k-h

Re: [External] Re: [PATCH v9 2/4] serial: 8250_dw: fix PSLVERR on RX_TIMEOUT

[John Ogness]

Added Douglas Anderson, author of commit 424d79183af0 ("serial: 8250_dw:
Avoid "too much work" from bogus rx timeout interrupt").

On 2025-07-11, yunhui cui <cuiyunhui@bytedance.com> wrote:
>> On 2025-06-23, yunhui cui <cuiyunhui@bytedance.com> wrote:
>> >> The DW UART may trigger the RX_TIMEOUT interrupt without data
>> >> present and remain stuck in this state indefinitely. The
>> >> dw8250_handle_irq() function detects this condition by checking
>> >> if the UART_LSR_DR bit is not set when RX_TIMEOUT occurs. When
>> >> detected, it performs a "dummy read" to recover the DW UART from
>> >> this state.
>> >>
>> >> When the PSLVERR_RESP_EN parameter is set to 1, reading the UART_RX
>> >> while the FIFO is enabled and UART_LSR_DR is not set will generate a
>> >> PSLVERR error, which may lead to a system panic. There are two methods
>> >> to prevent PSLVERR: one is to check if UART_LSR_DR is set before reading
>> >> UART_RX when the FIFO is enabled, and the other is to read UART_RX when
>> >> the FIFO is disabled.
>> >>
>> >> Given these two scenarios, the FIFO must be disabled before the
>> >> "dummy read" operation and re-enabled afterward to maintain normal
>> >> UART functionality.
>> >>
>> >> Fixes: 424d79183af0 ("serial: 8250_dw: Avoid "too much work" from bogus rx timeout interrupt")
>> >> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
>> >> Cc: stable@vger.kernel.org
>> >> ---
>> >>  drivers/tty/serial/8250/8250_dw.c | 10 +++++++++-
>> >>  1 file changed, 9 insertions(+), 1 deletion(-)
>> >>
>> >> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
>> >> index 1902f29444a1c..082b7fcf251db 100644
>> >> --- a/drivers/tty/serial/8250/8250_dw.c
>> >> +++ b/drivers/tty/serial/8250/8250_dw.c
>> >> @@ -297,9 +297,17 @@ static int dw8250_handle_irq(struct uart_port *p)
>> >>                 uart_port_lock_irqsave(p, &flags);
>> >>                 status = serial_lsr_in(up);
>> >>
>> >> -               if (!(status & (UART_LSR_DR | UART_LSR_BI)))
>> >> +               if (!(status & (UART_LSR_DR | UART_LSR_BI))) {
>> >> +                       /* To avoid PSLVERR, disable the FIFO first. */
>> >> +                       if (up->fcr & UART_FCR_ENABLE_FIFO)
>> >> +                               serial_out(up, UART_FCR, 0);
>> >> +
>> >>                         serial_port_in(p, UART_RX);
>> >>
>> >> +                       if (up->fcr & UART_FCR_ENABLE_FIFO)
>> >> +                               serial_out(up, UART_FCR, up->fcr);
>> >> +               }
>> >> +
>> >>                 uart_port_unlock_irqrestore(p, flags);
>> >>         }
>>
>> I do not know enough about the hardware. Is a dummy read really the only
>> way to exit the RX_TIMEOUT state?
>>
>> What if there are bytes in the TX-FIFO. Are they in danger of being
>> cleared?
>>
>> From [0] I see:
>>
>> "Writing a "0" to bit 0 will disable the FIFOs, in essence turning the
>>  UART into 8250 compatibility mode. In effect this also renders the rest
>>  of the settings in this register to become useless. If you write a "0"
>>  here it will also stop the FIFOs from sending or receiving data, so any
>>  data that is sent through the serial data port may be scrambled after
>>  this setting has been changed. It would be recommended to disable FIFOs
>>  only if you are trying to reset the serial communication protocol and
>>  clearing any working buffers you may have in your application
>>  software. Some documentation suggests that setting this bit to "0" also
>>  clears the FIFO buffers, but I would recommend explicit buffer clearing
>>  instead using bits 1 and 2."
>>
>> Have you performed tests where you fill the TX-FIFO and then
>> disable/enable the FIFO to see if the TX-bytes survive?
>
> Sorry, I haven't conducted relevant tests. The reason I made this
> modification is that it clearly contradicts the logic of avoiding
> PSLVERR. Disabling the FIFO can at least prevent the Panic() caused by
> PSVERR.

I am just wondering if there is some other way to avoid this. But since
we are talking about a hardware quirk and it is only related to
suspend/resume, maybe it is acceptable to risk data corruption in this
case. (?)

I am hoping Douglas can chime in.

John Ogness

>> [0] https://en.wikibooks.org/wiki/Serial_Programming/8250_UART_Programming

Re: [External] Re: [PATCH v9 2/4] serial: 8250_dw: fix PSLVERR on RX_TIMEOUT

[Doug Anderson]

Hi,

On Thu, Jul 17, 2025 at 7:14 AM John Ogness <john.ogness@linutronix.de> wrote:
>
> Added Douglas Anderson, author of commit 424d79183af0 ("serial: 8250_dw:
> Avoid "too much work" from bogus rx timeout interrupt").
>
> On 2025-07-11, yunhui cui <cuiyunhui@bytedance.com> wrote:
> >> On 2025-06-23, yunhui cui <cuiyunhui@bytedance.com> wrote:
> >> >> The DW UART may trigger the RX_TIMEOUT interrupt without data
> >> >> present and remain stuck in this state indefinitely. The
> >> >> dw8250_handle_irq() function detects this condition by checking
> >> >> if the UART_LSR_DR bit is not set when RX_TIMEOUT occurs. When
> >> >> detected, it performs a "dummy read" to recover the DW UART from
> >> >> this state.
> >> >>
> >> >> When the PSLVERR_RESP_EN parameter is set to 1, reading the UART_RX
> >> >> while the FIFO is enabled and UART_LSR_DR is not set will generate a
> >> >> PSLVERR error, which may lead to a system panic. There are two methods
> >> >> to prevent PSLVERR: one is to check if UART_LSR_DR is set before reading
> >> >> UART_RX when the FIFO is enabled, and the other is to read UART_RX when
> >> >> the FIFO is disabled.
> >> >>
> >> >> Given these two scenarios, the FIFO must be disabled before the
> >> >> "dummy read" operation and re-enabled afterward to maintain normal
> >> >> UART functionality.
> >> >>
> >> >> Fixes: 424d79183af0 ("serial: 8250_dw: Avoid "too much work" from bogus rx timeout interrupt")
> >> >> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> >> >> Cc: stable@vger.kernel.org
> >> >> ---
> >> >>  drivers/tty/serial/8250/8250_dw.c | 10 +++++++++-
> >> >>  1 file changed, 9 insertions(+), 1 deletion(-)
> >> >>
> >> >> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
> >> >> index 1902f29444a1c..082b7fcf251db 100644
> >> >> --- a/drivers/tty/serial/8250/8250_dw.c
> >> >> +++ b/drivers/tty/serial/8250/8250_dw.c
> >> >> @@ -297,9 +297,17 @@ static int dw8250_handle_irq(struct uart_port *p)
> >> >>                 uart_port_lock_irqsave(p, &flags);
> >> >>                 status = serial_lsr_in(up);
> >> >>
> >> >> -               if (!(status & (UART_LSR_DR | UART_LSR_BI)))
> >> >> +               if (!(status & (UART_LSR_DR | UART_LSR_BI))) {
> >> >> +                       /* To avoid PSLVERR, disable the FIFO first. */
> >> >> +                       if (up->fcr & UART_FCR_ENABLE_FIFO)
> >> >> +                               serial_out(up, UART_FCR, 0);
> >> >> +
> >> >>                         serial_port_in(p, UART_RX);
> >> >>
> >> >> +                       if (up->fcr & UART_FCR_ENABLE_FIFO)
> >> >> +                               serial_out(up, UART_FCR, up->fcr);
> >> >> +               }
> >> >> +
> >> >>                 uart_port_unlock_irqrestore(p, flags);
> >> >>         }
> >>
> >> I do not know enough about the hardware. Is a dummy read really the only
> >> way to exit the RX_TIMEOUT state?
> >>
> >> What if there are bytes in the TX-FIFO. Are they in danger of being
> >> cleared?
> >>
> >> From [0] I see:
> >>
> >> "Writing a "0" to bit 0 will disable the FIFOs, in essence turning the
> >>  UART into 8250 compatibility mode. In effect this also renders the rest
> >>  of the settings in this register to become useless. If you write a "0"
> >>  here it will also stop the FIFOs from sending or receiving data, so any
> >>  data that is sent through the serial data port may be scrambled after
> >>  this setting has been changed. It would be recommended to disable FIFOs
> >>  only if you are trying to reset the serial communication protocol and
> >>  clearing any working buffers you may have in your application
> >>  software. Some documentation suggests that setting this bit to "0" also
> >>  clears the FIFO buffers, but I would recommend explicit buffer clearing
> >>  instead using bits 1 and 2."
> >>
> >> Have you performed tests where you fill the TX-FIFO and then
> >> disable/enable the FIFO to see if the TX-bytes survive?
> >
> > Sorry, I haven't conducted relevant tests. The reason I made this
> > modification is that it clearly contradicts the logic of avoiding
> > PSLVERR. Disabling the FIFO can at least prevent the Panic() caused by
> > PSVERR.
>
> I am just wondering if there is some other way to avoid this. But since
> we are talking about a hardware quirk and it is only related to
> suspend/resume, maybe it is acceptable to risk data corruption in this
> case. (?)
>
> I am hoping Douglas can chime in.
>
> John Ogness
>
> >> [0] https://en.wikibooks.org/wiki/Serial_Programming/8250_UART_Programming

I'm not sure I have too much to add here. :( I did the investigation
and wrote the original patch over 8 years ago and I no longer have
access to the hardware where the problem first reproduced. I vaguely
remember the problem, but only because I re-read the commit message I
wrote 8 years ago. :-P

I will say that for the hardware I was working with, it wouldn't have
been the end of the world if there was a tiny bit of UART corruption
around suspend / resume. Of course, nothing about the workaround
specifically checks for suspend/resume, that was just how we were
reproducing problems. If there is ever any other way to get a "RX
timeout with no data" then we'd also potentially cause corruption with
the new patch. Still better than an interrupt storm or a panic,
though...

Not to say that I'm NAKing anything (since I'm a bit of a bystander in
this case), but I wonder if there's anything you could do better?
Ideas, maybe?

1. Could the PSLVERR be ignored in this case?

2. Could we temporarily disable generation of the PSLVERR for this read?

3. Could we detect when PSLVERR_RESP_EN=1 and only do the FIFO
disable/enable dance in that case?

-Doug