From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6C44186E27 for ; Mon, 28 Oct 2024 16:36:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730133395; cv=none; b=SmVBENqWAh8iPcnQakjh0JhHJXhhp3Vxk+sjS9at6w8PsMgC2D4BzKvelLLPvMQio4ZTHF8cbgUmyjcLSl4s+r24uFioAsx7o9erIrXmIpBdnbpZxHrdi7wiSeaAFOqwlFqYf5qk24f8gKOFVgtF3aYfWYgG2urdTMNFxjjqqRc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730133395; c=relaxed/simple; bh=lRA4coS4VvQXjSBy4sDjd0Bn4/FtKVlkuHePYaAhKGs=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=A9z2sovvuPo2PkYulzyp72rhCCXZNqOFVqW9iSZH97lC0p0HSnIxzJTywlmmEvNxE4OfLWn3UAI/Osh1YgW/1Prexc++8njz4oUmBVRsphREgZFORVQl03Y6HkqMQ5AmibYJb9HH3TxROnRoX5Lq3mRVsxjEt5JHS0g2hwOYLOs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=mAYB2V7s; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="mAYB2V7s" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730133393; x=1761669393; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=lRA4coS4VvQXjSBy4sDjd0Bn4/FtKVlkuHePYaAhKGs=; b=mAYB2V7sgzrpVOrhP3nJKR/y9gse/S+W7UgMDAm4VyAlE2MplilCyvOd mhf3MOtJzfxlJkY0i56A3+f2fvSyKuAuTnHnW0nxrBzGXjA1hO3v2CFFm sl1CHaNd1eqM08ddlKHR19WHXVxNE9q4/SMmjcDkfxFwU+TNeO0TnLmyG hxBPPuEv89175gnGss0/WmywXYEj7rbZwkt3deVZ9Xe5Z0PwDWZhaNCDF mTZp+020arNSelP8hNdB6/3Nrs3pbrnP8fhOyLCbsLqowkRinmAUme+0I vNtbmaUpaKqCFLggrNTfkuHeqV8+Bcbxz/lRIQ8uGQhOUpjgEbYmKAx9t Q==; X-CSE-ConnectionGUID: Um9YWGKISd+iYw9kLoNCAw== X-CSE-MsgGUID: a+/aiMqQSqm365ZVvMaUDA== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="40836449" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="40836449" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Oct 2024 09:36:33 -0700 X-CSE-ConnectionGUID: 8rqZ2eyiRXGL6p27hdAsgA== X-CSE-MsgGUID: t6iWll4VQZy2lMPNb+f8Zg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,239,1725346800"; d="scan'208";a="82481541" Received: from orsosgc001.jf.intel.com (HELO orsosgc001.intel.com) ([10.165.21.142]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Oct 2024 09:36:33 -0700 Date: Mon, 28 Oct 2024 09:36:32 -0700 Message-ID: <854j4wtca7.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Jonathan Cavitt Cc: intel-xe@lists.freedesktop.org, saurabhg.gupta@intel.com, alex.zuo@intel.com, umesh.nerlige.ramappa@intel.com, john.c.harrison@intel.com, stable@vger.kernel.org Subject: Re: [PATCH v3] drm/xe/xe_guc_ads: save/restore OA registers In-Reply-To: <20241023200716.82624-1-jonathan.cavitt@intel.com> References: <20241023200716.82624-1-jonathan.cavitt@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-redhat-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII On Wed, 23 Oct 2024 13:07:15 -0700, Jonathan Cavitt wrote: > Hi Umesh, > @@ -748,6 +754,14 @@ static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads, > } > } > > + guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL0, count++); > + guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL1, count++); > + guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL2, count++); > + guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL3, count++); > + guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL4, count++); > + guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL5, count++); > + guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL6, count++); I am trying to understand how this works. So these registers are saved/restored by GuC because they are not part of HW context image and that is why GuC needs to do the save/restore? Bspec 46458/56839 do seem to be saying that these registers are context saved/restored? If that is indeed true (though not sure), do they need to be here? Thanks. -- Ashutosh