From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5977200CB; Wed, 20 Nov 2024 08:18:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732090724; cv=none; b=PDO9hXfGF8JkIBZ1X36UP8q+EWzgGmiikx7t+VpDAMspGz0pskynFYH7/Uvfiatus7232l/1q+iYTmtOfEBwck3rGHZfNuyCvtxYmGM7uLcgRPaKTpmn5naKhh3LJt+Bc3FbAoV0eMKLWagkVv8cIo0VuuIMK9queEbVXBgQGX0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732090724; c=relaxed/simple; bh=8b23fimKmndiXTou2v0A2ca4nGlMAUjHBQGaAzvrsO0=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=s1YnsiZ4YpqKq8MzgQV2QJ9EAeQXz6PFWzg84M+DchG80Infb/mmbNx6H5Djq9Qhr3VpOyX1M5pxL1hpTGeCTT8FDKXMS9oz+eIVIi4VdB8skpFoncw+1nHRxBfYjhpbs5r6swAE7eM90TvkQXeH4eQ9q9fETCEXZRwZytGOof8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rn5TAIqp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rn5TAIqp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 69AD4C4CED0; Wed, 20 Nov 2024 08:18:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732090724; bh=8b23fimKmndiXTou2v0A2ca4nGlMAUjHBQGaAzvrsO0=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=rn5TAIqp1p/IXH31gLKRH4YNtlKqy087CpReAwzPXR3vj96sFQ8X9pu5dOH0r7bOF v7hJxbnxbTZ4kzEnwLw6ojhX6N/MjoSli/d30xP+WKgMMh9Tx92x2I7Utl/2rf9GPE PR+b+G8p300LgLnmvymtwSZvLVw6AkVWM+Row6yRcVrKy7lshkjaDXyPwughTd7ghV 2dvWXr7scgXMh5P71oC6mup7DJYXBIch8PsLlJKzQH2uCa8jofR5CBBj/K8Wi48MWh 25lW82QDCwSDCMq6k8TEQmW4sS1NadLa62CVtkfByWiJLKUD2+17D4/wKWy3tzxSV+ 1vCvM7cjKWr+w== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1tDfv6-00EOz6-3T; Wed, 20 Nov 2024 08:18:41 +0000 Date: Wed, 20 Nov 2024 08:18:39 +0000 Message-ID: <86v7wiuxls.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: kvmarm@lists.linux.dev, Joey Gouly , Suzuki K Poulose , Zenghui Yu , Mingwei Zhang , Colton Lewis , Raghavendra Rao Ananta , stable@vger.kernel.org Subject: Re: [PATCH v2 1/2] KVM: arm64: Ignore PMCNTENSET_EL0 while checking for overflow status In-Reply-To: <20241120005230.2335682-2-oliver.upton@linux.dev> References: <20241120005230.2335682-1-oliver.upton@linux.dev> <20241120005230.2335682-2-oliver.upton@linux.dev> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oliver.upton@linux.dev, kvmarm@lists.linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, mizhang@google.com, coltonlewis@google.com, rananta@google.com, stable@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Wed, 20 Nov 2024 00:52:29 +0000, Oliver Upton wrote: > > From: Raghavendra Rao Ananta > > DDI0487K D13.1.1 describes the PMU overflow condition, which evaluates nit: DDI0487K.a, and D13.3.1. > to true if any counter's global enable (PMCR_EL0.E), overflow flag > (PMOVSSET_EL0[n]), and interrupt enable (PMINTENSET_EL1[n]) are all 1. > Of note, this does not require a counter to be enabled > (i.e. PMCNTENSET_EL0[n] = 1) to generate an overflow. > > Align kvm_pmu_overflow_status() with the reality of the architecture > and stop using PMCNTENSET_EL0 as part of the overflow condition. The > bug was discovered while running an SBSA PMU test [*], which only sets > PMCR.E, PMOVSSET<0>, PMINTENSET<0>, and expects an overflow interrupt. > > Cc: stable@vger.kernel.org > Fixes: 76d883c4e640 ("arm64: KVM: Add access handler for PMOVSSET and PMOVSCLR register") > Link: https://github.com/ARM-software/sbsa-acs/blob/master/test_pool/pmu/operating_system/test_pmu001.c > Signed-off-by: Raghavendra Rao Ananta > [ oliver: massaged changelog ] > Signed-off-by: Oliver Upton > --- > arch/arm64/kvm/pmu-emul.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c > index 8ad62284fa23..3855cc9d0ca5 100644 > --- a/arch/arm64/kvm/pmu-emul.c > +++ b/arch/arm64/kvm/pmu-emul.c > @@ -381,7 +381,6 @@ static u64 kvm_pmu_overflow_status(struct kvm_vcpu *vcpu) > > if ((kvm_vcpu_read_pmcr(vcpu) & ARMV8_PMU_PMCR_E)) { > reg = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); > - reg &= __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); > reg &= __vcpu_sys_reg(vcpu, PMINTENSET_EL1); > } > Reviewed-by: Marc Zyngier M. -- Without deviation from the norm, progress is not possible.