From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com ([192.55.52.93]:46602 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751033AbcJJJEl (ORCPT ); Mon, 10 Oct 2016 05:04:41 -0400 From: Jani Nikula To: Paulo Zanoni , intel-gfx@lists.freedesktop.org Cc: dhinakaran.pandiyan@intel.com, stable@vger.kernel.org, Paulo Zanoni Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/gen9: fix watermarks when using the pipe scaler In-Reply-To: <1475872138-16194-1-git-send-email-paulo.r.zanoni@intel.com> References: <1475872138-16194-1-git-send-email-paulo.r.zanoni@intel.com> Date: Mon, 10 Oct 2016 12:01:35 +0300 Message-ID: <8737k4tw5s.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain Sender: stable-owner@vger.kernel.org List-ID: On Fri, 07 Oct 2016, Paulo Zanoni wrote: > Luckily, the necessary adjustments for when we're using the scaler are > exactly the same as the ones needed on ILK+, so just reuse the > function we already have. > > v2: Invert the patch order so stable backports get easier. Replied to the other set first... this order is fine too, with or without cc: stable on the other one. BR, Jani. > > Cc: stable@vger.kernel.org > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/intel_pm.c | 12 +++--------- > 1 file changed, 3 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index fe6c1c6..000b033 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3470,12 +3470,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate, > return 0; > } > > -static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config) > -{ > - /* TODO: Take into account the scalers once we support them */ > - return config->base.adjusted_mode.crtc_clock; > -} > - > /* > * The max latency should be 257 (max the punit can code is 255 and we add 2us > * for the read latency) and cpp should always be <= 8, so that > @@ -3526,7 +3520,7 @@ static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cst > * Adjusted plane pixel rate is just the pipe's adjusted pixel rate > * with additional adjustments for plane-specific scaling. > */ > - adjusted_pixel_rate = skl_pipe_pixel_rate(cstate); > + adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate); > downscale_amount = skl_plane_downscale_amount(pstate); > > pixel_rate = adjusted_pixel_rate * downscale_amount >> 16; > @@ -3742,11 +3736,11 @@ skl_compute_linetime_wm(struct intel_crtc_state *cstate) > if (!cstate->base.active) > return 0; > > - if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0)) > + if (WARN_ON(ilk_pipe_pixel_rate(cstate) == 0)) > return 0; > > return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000, > - skl_pipe_pixel_rate(cstate)); > + ilk_pipe_pixel_rate(cstate)); > } > > static void skl_compute_transition_wm(struct intel_crtc_state *cstate, -- Jani Nikula, Intel Open Source Technology Center