From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86F882BDC0B; Thu, 26 Feb 2026 08:17:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772093820; cv=none; b=ueoT9xMc6ykp3Fme2sA0rhNOY/jzwUvnRGVsdKnicF/PrIpRR7TYGdd4rpDwA7XrOKF0gFxK59Dcq+PKKRPVOZ5A9R2aIdqYkWW/ZorpajYfKXOpv/jKv6Jcvfwb5yt7XfWqQozkQWVjtGvj71ZXIvHgfMfrhswj1gUBmCLYmLE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772093820; c=relaxed/simple; bh=+gGBp2tFSvf9ce8ZvXdjbIa0L0e347XIZ5YgOecuN1E=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=sln4x5WX9a6DgPxRspT/M3ptlivzMyxgOFJHeTQ4bqjL8vjWxqvbl9gAzwuXBzhOluXKTcJW9mVnWUwHEh3FiTUSHsssRPM67+mvhULkEb/DnFf01g/uJFJqNC+xdwcOAGWY6fWROB3OiSTT/7bWAENYFaQf40YV0HcyskOdbp0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JWKt/VXI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JWKt/VXI" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 21243C19422; Thu, 26 Feb 2026 08:17:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772093820; bh=+gGBp2tFSvf9ce8ZvXdjbIa0L0e347XIZ5YgOecuN1E=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=JWKt/VXIwAnGoCw1JoMUNsqfRXjZWNLQOkcf74f8OPA44n2im9gOibpDVlNRLX6LE uXPzxdOwtjPFwo9k6Y3b4kAIpG4tiK87QuZdI9Y+eoP5hSkWjxUfGZC4C50GZkF0D4 DmIBadyVsRFjM9WPu+KY1j65NlY/RAczskDdlSiFU0pHXVjGDSu7k1i9W83rqELOTI jmob44SWNaGvdXpx9FH0EmELozbMhEZiCXJdKSqsoFoUBaIX5BgKCBfGywzucl68im R/3LGzhznoBoq9HkFMYDUqDKygSANei0fyfoaZfN+DGP33urN8dz5QaSvBd7Ptiiky 8xNcIB5ZWazmw== Received: from sofa.misterjones.org ([185.219.108.64] helo=lobster-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vvWYL-0000000DyCT-2KqH; Thu, 26 Feb 2026 08:16:57 +0000 Date: Thu, 26 Feb 2026 08:16:57 +0000 Message-ID: <875x7jex6u.wl-maz@kernel.org> From: Marc Zyngier To: Will Deacon Cc: Ben Horgan , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Catalin Marinas , Hyesoo Yu , Quentin Perret , stable@vger.kernel.org Subject: Re: [PATCH] arm64: Force the use of CNTVCT_EL0 in __delay() In-Reply-To: References: <20260213141619.1791283-1-maz@kernel.org> <86ldgja5v3.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: will@kernel.org, ben.horgan@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, oupton@kernel.org, yuzenghui@huawei.com, catalin.marinas@arm.com, hyesoo.yu@samsung.com, qperret@google.com, stable@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Wed, 25 Feb 2026 22:36:07 +0000, Will Deacon wrote: > > On Mon, Feb 23, 2026 at 02:31:44PM +0000, Marc Zyngier wrote: > > Crucially, arch_counter_get_cntvct_stable() does disable preemption, > > and we should preserve it. Something like this: > > > > diff --git a/arch/arm64/lib/delay.c b/arch/arm64/lib/delay.c > > index d02341303899e..25fb593f95b0c 100644 > > --- a/arch/arm64/lib/delay.c > > +++ b/arch/arm64/lib/delay.c > > @@ -32,7 +32,16 @@ static inline unsigned long xloops_to_cycles(unsigned long xloops) > > * Note that userspace cannot change the offset behind our back either, > > * as the vcpu mutex is held as long as KVM_RUN is in progress. > > */ > > -#define __delay_cycles() __arch_counter_get_cntvct_stable() > > +static cycles_t __delay_cycles(void) > > +{ > > + cycles_t val; > > + > > + preempt_disable(); > > + val = __arch_counter_get_cntvct_stable(); > > + preenpt_enable(); > > + > > + return val; > > +} > > (nit: arch_counter_get_cntvct_stable() uses the _notrace() variants of > the preempt disable/enable helpers) That's because arch_counter_get_cntvct_stable() itself is notrace. I'm not sure we need this function to be notrace as well, but I'll change that and we can revisit it. > > > void __delay(unsigned long cycles) > > { > > > > The question is whether there is a material benefit in replicating the > > arch_timer_read_counter() indirection for the virtual counter in order > > to not pay the price of preempt_disable() when we're on a non-broken > > system (hopefully the vast majority of implementations). > > That sounds nice, especially as we can assume (for now) that CPUs > implementing WFIT don't need the cntvct workarounds. However, I can't > really figure out how to implement it after reminding myself of all the > fun we had trying to use a static key for these workarounds in the past. > > If a CPU being onlined has a timer erratum, we wouldn't be able to > migrate any tasks in the middle of a preempt-enabled delay loop onto > it. :/ Why would it be any different than, say, sched_clock(), which ultimately uses arch_timer_read_counter()? We already rely on this indirection to do the right thing everywhere, and I don't recall we have any issue with this. Anyway, I'll shortly post what I have and we can discuss whether this is the correct approach. Thanks, M. -- Jazz isn't dead. It just smells funny.