From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7A18C2BB55 for ; Wed, 15 Apr 2020 11:12:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C27A120737 for ; Wed, 15 Apr 2020 11:12:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2896779AbgDOLLt (ORCPT ); Wed, 15 Apr 2020 07:11:49 -0400 Received: from mga18.intel.com ([134.134.136.126]:6920 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2896754AbgDOLLj (ORCPT ); Wed, 15 Apr 2020 07:11:39 -0400 IronPort-SDR: LVf3c91CMstKsFtm0AQXE0LxDXX6omwBuylh53LK4GdlR6J1EnKjAbxouQ/JXRHlzJitNhyUve cG6I2AeXu3pg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Apr 2020 04:11:02 -0700 IronPort-SDR: m784YejBeSGPC4uUll48KfJugWat0l1mlLktWdHH8pxDn013ofHBIaKHoM7AZzX9rcj6zDgRKU h0BrXbORmCtA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,386,1580803200"; d="scan'208";a="256825955" Received: from gaia.fi.intel.com ([10.237.72.192]) by orsmga006.jf.intel.com with ESMTP; 15 Apr 2020 04:11:00 -0700 Received: by gaia.fi.intel.com (Postfix, from userid 1000) id 0316E5C1DA7; Wed, 15 Apr 2020 14:09:10 +0300 (EEST) From: Mika Kuoppala To: Chris Wilson , intel-gfx@lists.freedesktop.org Cc: Chris Wilson , Francisco Jerez , Andi Shyti , stable@vger.kernel.org Subject: Re: [PATCH] drm/i915/gt: Update PMINTRMSK holding fw In-Reply-To: <20200415075018.7636-1-chris@chris-wilson.co.uk> References: <20200415075018.7636-1-chris@chris-wilson.co.uk> Date: Wed, 15 Apr 2020 14:09:10 +0300 Message-ID: <875ze1ngyx.fsf@gaia.fi.intel.com> MIME-Version: 1.0 Content-Type: text/plain Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org Chris Wilson writes: > If we use a non-forcewaked write to PMINTRMSK, it does not take effect > until much later, if at all, causing a loss of RPS interrupts and no GPU > reclocking, leaving the GPU running at the wrong frequency for long > periods of time. > > Reported-by: Francisco Jerez > Suggested-by: Francisco Jerez > Fixes: 35cc7f32c298 ("drm/i915/gt: Use non-forcewake writes for RPS") > Signed-off-by: Chris Wilson > Cc: Francisco Jerez > Cc: Mika Kuoppala > Cc: Andi Shyti > Cc: # v5.6+ Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/gt/intel_rps.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c > index 86110458e2a7..6a3505467406 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rps.c > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c > @@ -81,13 +81,14 @@ static void rps_enable_interrupts(struct intel_rps *rps) > events = (GEN6_PM_RP_UP_THRESHOLD | > GEN6_PM_RP_DOWN_THRESHOLD | > GEN6_PM_RP_DOWN_TIMEOUT); > - > WRITE_ONCE(rps->pm_events, events); > + > spin_lock_irq(>->irq_lock); > gen6_gt_pm_enable_irq(gt, rps->pm_events); > spin_unlock_irq(>->irq_lock); > > - set(gt->uncore, GEN6_PMINTRMSK, rps_pm_mask(rps, rps->cur_freq)); > + intel_uncore_write(gt->uncore, > + GEN6_PMINTRMSK, rps_pm_mask(rps, rps->last_freq)); > } > > static void gen6_rps_reset_interrupts(struct intel_rps *rps) > @@ -120,7 +121,9 @@ static void rps_disable_interrupts(struct intel_rps *rps) > struct intel_gt *gt = rps_to_gt(rps); > > WRITE_ONCE(rps->pm_events, 0); > - set(gt->uncore, GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u)); > + > + intel_uncore_write(gt->uncore, > + GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u)); > > spin_lock_irq(>->irq_lock); > gen6_gt_pm_disable_irq(gt, GEN6_PM_RPS_EVENTS); > -- > 2.20.1