* [PATCH 1/2] drm/i915: Restore lost DPLL register write on gen2-4
@ 2015-10-07 19:08 ville.syrjala
2015-10-08 8:17 ` [Intel-gfx] " Daniel Vetter
0 siblings, 1 reply; 6+ messages in thread
From: ville.syrjala @ 2015-10-07 19:08 UTC (permalink / raw)
To: intel-gfx; +Cc: stable, Nick Bowler
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We accidentally lost the initial DPLL register write in
1c4e02746147 drm/i915: Fix DVO 2x clock enable on 830M
The "three times for luck" hack probably saved us from a total
disaster. But anyway, bring the initial write back so that the
code actually makes some sense.
Cc: stable@vger.kernel.org
Cc: Nick Bowler <nbowler@draconx.ca>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 147e700..f4fdff9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1743,6 +1743,8 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
}
+ I915_WRITE(reg, dpll);
+
/* Wait for the clocks to stabilize. */
POSTING_READ(reg);
udelay(150);
--
2.4.9
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915: Restore lost DPLL register write on gen2-4
2015-10-07 19:08 [PATCH 1/2] drm/i915: Restore lost DPLL register write on gen2-4 ville.syrjala
@ 2015-10-08 8:17 ` Daniel Vetter
2015-10-08 8:18 ` Ville Syrjälä
0 siblings, 1 reply; 6+ messages in thread
From: Daniel Vetter @ 2015-10-08 8:17 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx, Nick Bowler, stable
On Wed, Oct 07, 2015 at 10:08:24PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrj�l� <ville.syrjala@linux.intel.com>
>
> We accidentally lost the initial DPLL register write in
> 1c4e02746147 drm/i915: Fix DVO 2x clock enable on 830M
>
> The "three times for luck" hack probably saved us from a total
> disaster. But anyway, bring the initial write back so that the
> code actually makes some sense.
>
> Cc: stable@vger.kernel.org
> Cc: Nick Bowler <nbowler@draconx.ca>
Reported-and-tested-by: Nick Bowler <nbowler@draconx.ca>
References: http://lists.freedesktop.org/archives/intel-gfx/2015-October/077463.html
> Signed-off-by: Ville Syrj�l� <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 147e700..f4fdff9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1743,6 +1743,8 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
> I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
Don't we also need a POSTING_READ here to make sure the two-step 2x mode
sequence is still followed?
With that addressed Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> }
>
> + I915_WRITE(reg, dpll);
> +
> /* Wait for the clocks to stabilize. */
> POSTING_READ(reg);
> udelay(150);
> --
> 2.4.9
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915: Restore lost DPLL register write on gen2-4
2015-10-08 8:17 ` [Intel-gfx] " Daniel Vetter
@ 2015-10-08 8:18 ` Ville Syrjälä
2015-10-13 13:10 ` Jani Nikula
0 siblings, 1 reply; 6+ messages in thread
From: Ville Syrjälä @ 2015-10-08 8:18 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx, Nick Bowler, stable
On Thu, Oct 08, 2015 at 10:17:30AM +0200, Daniel Vetter wrote:
> On Wed, Oct 07, 2015 at 10:08:24PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrj�l� <ville.syrjala@linux.intel.com>
> >
> > We accidentally lost the initial DPLL register write in
> > 1c4e02746147 drm/i915: Fix DVO 2x clock enable on 830M
> >
> > The "three times for luck" hack probably saved us from a total
> > disaster. But anyway, bring the initial write back so that the
> > code actually makes some sense.
> >
> > Cc: stable@vger.kernel.org
> > Cc: Nick Bowler <nbowler@draconx.ca>
> Reported-and-tested-by: Nick Bowler <nbowler@draconx.ca>
> References: http://lists.freedesktop.org/archives/intel-gfx/2015-October/077463.html
>
> > Signed-off-by: Ville Syrj�l� <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 147e700..f4fdff9 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1743,6 +1743,8 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
> > I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
>
> Don't we also need a POSTING_READ here to make sure the two-step 2x mode
> sequence is still followed?
We don't do write combining on registers, and there are no shadow
register type of things to consider in this case either.
>
> With that addressed Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > }
> >
> > + I915_WRITE(reg, dpll);
> > +
> > /* Wait for the clocks to stabilize. */
> > POSTING_READ(reg);
> > udelay(150);
> > --
> > 2.4.9
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
--
Ville Syrj�l�
Intel OTC
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915: Restore lost DPLL register write on gen2-4
2015-10-08 8:18 ` Ville Syrjälä
@ 2015-10-13 13:10 ` Jani Nikula
2015-10-13 13:56 ` Daniel Vetter
0 siblings, 1 reply; 6+ messages in thread
From: Jani Nikula @ 2015-10-13 13:10 UTC (permalink / raw)
To: Ville Syrjälä, Daniel Vetter; +Cc: Nick Bowler, intel-gfx, stable
On Thu, 08 Oct 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Oct 08, 2015 at 10:17:30AM +0200, Daniel Vetter wrote:
>> On Wed, Oct 07, 2015 at 10:08:24PM +0300, ville.syrjala@linux.intel.com wrote:
>> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >
>> > We accidentally lost the initial DPLL register write in
>> > 1c4e02746147 drm/i915: Fix DVO 2x clock enable on 830M
>> >
>> > The "three times for luck" hack probably saved us from a total
>> > disaster. But anyway, bring the initial write back so that the
>> > code actually makes some sense.
>> >
>> > Cc: stable@vger.kernel.org
>> > Cc: Nick Bowler <nbowler@draconx.ca>
>> Reported-and-tested-by: Nick Bowler <nbowler@draconx.ca>
>> References: http://lists.freedesktop.org/archives/intel-gfx/2015-October/077463.html
>>
>> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > ---
>> > drivers/gpu/drm/i915/intel_display.c | 2 ++
>> > 1 file changed, 2 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> > index 147e700..f4fdff9 100644
>> > --- a/drivers/gpu/drm/i915/intel_display.c
>> > +++ b/drivers/gpu/drm/i915/intel_display.c
>> > @@ -1743,6 +1743,8 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
>> > I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
>>
>> Don't we also need a POSTING_READ here to make sure the two-step 2x mode
>> sequence is still followed?
>
> We don't do write combining on registers, and there are no shadow
> register type of things to consider in this case either.
>
>>
>> With that addressed Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel, are you happy with the responses about posting reads, for both
patches?
BR,
Jani.
>> > }
>> >
>> > + I915_WRITE(reg, dpll);
>> > +
>> > /* Wait for the clocks to stabilize. */
>> > POSTING_READ(reg);
>> > udelay(150);
>> > --
>> > 2.4.9
>> >
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>> --
>> Daniel Vetter
>> Software Engineer, Intel Corporation
>> http://blog.ffwll.ch
>
> --
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915: Restore lost DPLL register write on gen2-4
2015-10-13 13:10 ` Jani Nikula
@ 2015-10-13 13:56 ` Daniel Vetter
2015-10-13 14:07 ` Jani Nikula
0 siblings, 1 reply; 6+ messages in thread
From: Daniel Vetter @ 2015-10-13 13:56 UTC (permalink / raw)
To: Jani Nikula
Cc: Ville Syrjälä, Daniel Vetter, Nick Bowler, intel-gfx,
stable
On Tue, Oct 13, 2015 at 04:10:19PM +0300, Jani Nikula wrote:
> On Thu, 08 Oct 2015, Ville Syrj�l� <ville.syrjala@linux.intel.com> wrote:
> > On Thu, Oct 08, 2015 at 10:17:30AM +0200, Daniel Vetter wrote:
> >> On Wed, Oct 07, 2015 at 10:08:24PM +0300, ville.syrjala@linux.intel.com wrote:
> >> > From: Ville Syrj�l� <ville.syrjala@linux.intel.com>
> >> >
> >> > We accidentally lost the initial DPLL register write in
> >> > 1c4e02746147 drm/i915: Fix DVO 2x clock enable on 830M
> >> >
> >> > The "three times for luck" hack probably saved us from a total
> >> > disaster. But anyway, bring the initial write back so that the
> >> > code actually makes some sense.
> >> >
> >> > Cc: stable@vger.kernel.org
> >> > Cc: Nick Bowler <nbowler@draconx.ca>
> >> Reported-and-tested-by: Nick Bowler <nbowler@draconx.ca>
> >> References: http://lists.freedesktop.org/archives/intel-gfx/2015-October/077463.html
> >>
> >> > Signed-off-by: Ville Syrj�l� <ville.syrjala@linux.intel.com>
> >> > ---
> >> > drivers/gpu/drm/i915/intel_display.c | 2 ++
> >> > 1 file changed, 2 insertions(+)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> >> > index 147e700..f4fdff9 100644
> >> > --- a/drivers/gpu/drm/i915/intel_display.c
> >> > +++ b/drivers/gpu/drm/i915/intel_display.c
> >> > @@ -1743,6 +1743,8 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
> >> > I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
> >>
> >> Don't we also need a POSTING_READ here to make sure the two-step 2x mode
> >> sequence is still followed?
> >
> > We don't do write combining on registers, and there are no shadow
> > register type of things to consider in this case either.
> >
> >>
> >> With that addressed Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>
>
> Daniel, are you happy with the responses about posting reads, for both
> patches?
Yeah, acked on irc but forgot to follow up.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915: Restore lost DPLL register write on gen2-4
2015-10-13 13:56 ` Daniel Vetter
@ 2015-10-13 14:07 ` Jani Nikula
0 siblings, 0 replies; 6+ messages in thread
From: Jani Nikula @ 2015-10-13 14:07 UTC (permalink / raw)
To: Daniel Vetter
Cc: Ville Syrjälä, Daniel Vetter, Nick Bowler, intel-gfx,
stable
On Tue, 13 Oct 2015, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Tue, Oct 13, 2015 at 04:10:19PM +0300, Jani Nikula wrote:
>> On Thu, 08 Oct 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
>> > On Thu, Oct 08, 2015 at 10:17:30AM +0200, Daniel Vetter wrote:
>> >> On Wed, Oct 07, 2015 at 10:08:24PM +0300, ville.syrjala@linux.intel.com wrote:
>> >> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >> >
>> >> > We accidentally lost the initial DPLL register write in
>> >> > 1c4e02746147 drm/i915: Fix DVO 2x clock enable on 830M
>> >> >
>> >> > The "three times for luck" hack probably saved us from a total
>> >> > disaster. But anyway, bring the initial write back so that the
>> >> > code actually makes some sense.
>> >> >
>> >> > Cc: stable@vger.kernel.org
>> >> > Cc: Nick Bowler <nbowler@draconx.ca>
>> >> Reported-and-tested-by: Nick Bowler <nbowler@draconx.ca>
>> >> References: http://lists.freedesktop.org/archives/intel-gfx/2015-October/077463.html
>> >>
>> >> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >> > ---
>> >> > drivers/gpu/drm/i915/intel_display.c | 2 ++
>> >> > 1 file changed, 2 insertions(+)
>> >> >
>> >> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> >> > index 147e700..f4fdff9 100644
>> >> > --- a/drivers/gpu/drm/i915/intel_display.c
>> >> > +++ b/drivers/gpu/drm/i915/intel_display.c
>> >> > @@ -1743,6 +1743,8 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
>> >> > I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
>> >>
>> >> Don't we also need a POSTING_READ here to make sure the two-step 2x mode
>> >> sequence is still followed?
>> >
>> > We don't do write combining on registers, and there are no shadow
>> > register type of things to consider in this case either.
>> >
>> >>
>> >> With that addressed Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>>
>>
>> Daniel, are you happy with the responses about posting reads, for both
>> patches?
>
> Yeah, acked on irc but forgot to follow up.
Both pushed to drm-intel-fixes, thanks for the patches and review.
BR,
Jani.
> -Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2015-10-13 14:05 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2015-10-07 19:08 [PATCH 1/2] drm/i915: Restore lost DPLL register write on gen2-4 ville.syrjala
2015-10-08 8:17 ` [Intel-gfx] " Daniel Vetter
2015-10-08 8:18 ` Ville Syrjälä
2015-10-13 13:10 ` Jani Nikula
2015-10-13 13:56 ` Daniel Vetter
2015-10-13 14:07 ` Jani Nikula
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