* [PATCH] drm/i915: Flush pipecontrol post-sync writes
@ 2015-08-21 15:08 Chris Wilson
2015-08-21 15:21 ` [Intel-gfx] " Ville Syrjälä
2015-08-26 9:16 ` Daniel Vetter
0 siblings, 2 replies; 7+ messages in thread
From: Chris Wilson @ 2015-08-21 15:08 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson, stable
In order to flush the results from in-batch pipecontrol writes (used for
example in glQuery) before declaring the batch complete (and so declaring
the query results coherent), we need to set the FlushEnable bit in our
flushing pipecontrol. The FlushEnable bit "waits until all previous
writes of immediate data from post-sync circles are complete before
executing the next command".
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@vger.kernel.org
---
drivers/gpu/drm/i915/intel_lrc.c | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 01cf0ca21990..e0c19d75b196 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1771,6 +1771,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
if (flush_domains) {
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
+ flags |= PIPE_CONTROL_FLUSH_ENABLE;
}
if (invalidate_domains) {
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c2392f6c4204..551af7399ca1 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -330,6 +330,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
if (flush_domains) {
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
+ flags |= PIPE_CONTROL_FLUSH_ENABLE;
}
if (invalidate_domains) {
flags |= PIPE_CONTROL_TLB_INVALIDATE;
@@ -401,6 +402,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
if (flush_domains) {
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
+ flags |= PIPE_CONTROL_FLUSH_ENABLE;
}
if (invalidate_domains) {
flags |= PIPE_CONTROL_TLB_INVALIDATE;
--
2.5.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [Intel-gfx] [PATCH] drm/i915: Flush pipecontrol post-sync writes
2015-08-21 15:08 [PATCH] drm/i915: Flush pipecontrol post-sync writes Chris Wilson
@ 2015-08-21 15:21 ` Ville Syrjälä
2015-08-26 9:16 ` Daniel Vetter
1 sibling, 0 replies; 7+ messages in thread
From: Ville Syrjälä @ 2015-08-21 15:21 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx, stable
On Fri, Aug 21, 2015 at 04:08:41PM +0100, Chris Wilson wrote:
> In order to flush the results from in-batch pipecontrol writes (used for
> example in glQuery) before declaring the batch complete (and so declaring
> the query results coherent), we need to set the FlushEnable bit in our
> flushing pipecontrol. The FlushEnable bit "waits until all previous
> writes of immediate data from post-sync circles are complete before
> executing the next command".
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: stable@vger.kernel.org
Yeah makes as much sense as anything about pipecontrols.
Reviewed-by: Ville Syrj�l� <ville.syrjala@linux.intel.com>
Though the spec makes me thing it would be even more appropriate if
we did the seqno write using a post-sync operation and followed it
with such a pipecontrol flush. But I've not actually played around
with this stuff, so can't say for sure.
Oh and we're also lacking DC flushes everywhere, in case someone
cares.
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 1 +
> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 01cf0ca21990..e0c19d75b196 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1771,6 +1771,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
>
> if (invalidate_domains) {
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index c2392f6c4204..551af7399ca1 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -330,6 +330,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
> if (invalidate_domains) {
> flags |= PIPE_CONTROL_TLB_INVALIDATE;
> @@ -401,6 +402,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
> if (invalidate_domains) {
> flags |= PIPE_CONTROL_TLB_INVALIDATE;
> --
> 2.5.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrj�l�
Intel OTC
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [Intel-gfx] [PATCH] drm/i915: Flush pipecontrol post-sync writes
2015-08-21 15:08 [PATCH] drm/i915: Flush pipecontrol post-sync writes Chris Wilson
2015-08-21 15:21 ` [Intel-gfx] " Ville Syrjälä
@ 2015-08-26 9:16 ` Daniel Vetter
2015-08-26 9:29 ` Chris Wilson
1 sibling, 1 reply; 7+ messages in thread
From: Daniel Vetter @ 2015-08-26 9:16 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx, stable
On Fri, Aug 21, 2015 at 04:08:41PM +0100, Chris Wilson wrote:
> In order to flush the results from in-batch pipecontrol writes (used for
> example in glQuery) before declaring the batch complete (and so declaring
> the query results coherent), we need to set the FlushEnable bit in our
> flushing pipecontrol. The FlushEnable bit "waits until all previous
> writes of immediate data from post-sync circles are complete before
> executing the next command".
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: stable@vger.kernel.org
Do we have an igt/piglit failing somewhere (igt kinda preferred) or a
bugzilla or why is this cc: stable?
-Daniel
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 1 +
> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 01cf0ca21990..e0c19d75b196 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1771,6 +1771,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
>
> if (invalidate_domains) {
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index c2392f6c4204..551af7399ca1 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -330,6 +330,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
> if (invalidate_domains) {
> flags |= PIPE_CONTROL_TLB_INVALIDATE;
> @@ -401,6 +402,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
> if (invalidate_domains) {
> flags |= PIPE_CONTROL_TLB_INVALIDATE;
> --
> 2.5.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [Intel-gfx] [PATCH] drm/i915: Flush pipecontrol post-sync writes
2015-08-26 9:16 ` Daniel Vetter
@ 2015-08-26 9:29 ` Chris Wilson
2015-10-13 12:45 ` Jani Nikula
0 siblings, 1 reply; 7+ messages in thread
From: Chris Wilson @ 2015-08-26 9:29 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx, stable
On Wed, Aug 26, 2015 at 11:16:34AM +0200, Daniel Vetter wrote:
> On Fri, Aug 21, 2015 at 04:08:41PM +0100, Chris Wilson wrote:
> > In order to flush the results from in-batch pipecontrol writes (used for
> > example in glQuery) before declaring the batch complete (and so declaring
> > the query results coherent), we need to set the FlushEnable bit in our
> > flushing pipecontrol. The FlushEnable bit "waits until all previous
> > writes of immediate data from post-sync circles are complete before
> > executing the next command".
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: stable@vger.kernel.org
>
> Do we have an igt/piglit failing somewhere (igt kinda preferred) or a
> bugzilla or why is this cc: stable?
I get GPU hangs on byt without flushing these writes (running ue4).
piglit has examples where the flush is required for correct rendering.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Flush pipecontrol post-sync writes
2015-08-26 9:29 ` Chris Wilson
@ 2015-10-13 12:45 ` Jani Nikula
2015-10-13 13:37 ` Daniel Vetter
0 siblings, 1 reply; 7+ messages in thread
From: Jani Nikula @ 2015-10-13 12:45 UTC (permalink / raw)
To: Chris Wilson, Daniel Vetter; +Cc: intel-gfx, stable
On Wed, 26 Aug 2015, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> On Wed, Aug 26, 2015 at 11:16:34AM +0200, Daniel Vetter wrote:
>> On Fri, Aug 21, 2015 at 04:08:41PM +0100, Chris Wilson wrote:
>> > In order to flush the results from in-batch pipecontrol writes (used for
>> > example in glQuery) before declaring the batch complete (and so declaring
>> > the query results coherent), we need to set the FlushEnable bit in our
>> > flushing pipecontrol. The FlushEnable bit "waits until all previous
>> > writes of immediate data from post-sync circles are complete before
>> > executing the next command".
>> >
>> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>> > Cc: stable@vger.kernel.org
>>
>> Do we have an igt/piglit failing somewhere (igt kinda preferred) or a
>> bugzilla or why is this cc: stable?
>
> I get GPU hangs on byt without flushing these writes (running ue4).
> piglit has examples where the flush is required for correct rendering.
Daniel, does this satisfy your question? We've had an r-b from Ville for
a long time.
BR,
Jani.
> -Chris
>
> --
> Chris Wilson, Intel Open Source Technology Centre
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Flush pipecontrol post-sync writes
2015-10-13 12:45 ` Jani Nikula
@ 2015-10-13 13:37 ` Daniel Vetter
2015-10-13 13:57 ` Jani Nikula
0 siblings, 1 reply; 7+ messages in thread
From: Daniel Vetter @ 2015-10-13 13:37 UTC (permalink / raw)
To: Jani Nikula; +Cc: Chris Wilson, Daniel Vetter, intel-gfx, stable
On Tue, Oct 13, 2015 at 03:45:58PM +0300, Jani Nikula wrote:
> On Wed, 26 Aug 2015, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > On Wed, Aug 26, 2015 at 11:16:34AM +0200, Daniel Vetter wrote:
> >> On Fri, Aug 21, 2015 at 04:08:41PM +0100, Chris Wilson wrote:
> >> > In order to flush the results from in-batch pipecontrol writes (used for
> >> > example in glQuery) before declaring the batch complete (and so declaring
> >> > the query results coherent), we need to set the FlushEnable bit in our
> >> > flushing pipecontrol. The FlushEnable bit "waits until all previous
> >> > writes of immediate data from post-sync circles are complete before
> >> > executing the next command".
> >> >
> >> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> >> > Cc: stable@vger.kernel.org
> >>
> >> Do we have an igt/piglit failing somewhere (igt kinda preferred) or a
> >> bugzilla or why is this cc: stable?
> >
> > I get GPU hangs on byt without flushing these writes (running ue4).
> > piglit has examples where the flush is required for correct rendering.
>
> Daniel, does this satisfy your question? We've had an r-b from Ville for
> a long time.
Yeah, just add that bit to the commit message to justify cc: stable.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Flush pipecontrol post-sync writes
2015-10-13 13:37 ` Daniel Vetter
@ 2015-10-13 13:57 ` Jani Nikula
0 siblings, 0 replies; 7+ messages in thread
From: Jani Nikula @ 2015-10-13 13:57 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Chris Wilson, Daniel Vetter, intel-gfx, stable
On Tue, 13 Oct 2015, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Tue, Oct 13, 2015 at 03:45:58PM +0300, Jani Nikula wrote:
>> On Wed, 26 Aug 2015, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>> > On Wed, Aug 26, 2015 at 11:16:34AM +0200, Daniel Vetter wrote:
>> >> On Fri, Aug 21, 2015 at 04:08:41PM +0100, Chris Wilson wrote:
>> >> > In order to flush the results from in-batch pipecontrol writes (used for
>> >> > example in glQuery) before declaring the batch complete (and so declaring
>> >> > the query results coherent), we need to set the FlushEnable bit in our
>> >> > flushing pipecontrol. The FlushEnable bit "waits until all previous
>> >> > writes of immediate data from post-sync circles are complete before
>> >> > executing the next command".
>> >> >
>> >> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>> >> > Cc: stable@vger.kernel.org
>> >>
>> >> Do we have an igt/piglit failing somewhere (igt kinda preferred) or a
>> >> bugzilla or why is this cc: stable?
>> >
>> > I get GPU hangs on byt without flushing these writes (running ue4).
>> > piglit has examples where the flush is required for correct rendering.
>>
>> Daniel, does this satisfy your question? We've had an r-b from Ville for
>> a long time.
>
> Yeah, just add that bit to the commit message to justify cc: stable.
Pushed to drm-intel-fixes, thanks for the patch and review.
BR,
Jani.
> -Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 7+ messages in thread
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2015-08-21 15:08 [PATCH] drm/i915: Flush pipecontrol post-sync writes Chris Wilson
2015-08-21 15:21 ` [Intel-gfx] " Ville Syrjälä
2015-08-26 9:16 ` Daniel Vetter
2015-08-26 9:29 ` Chris Wilson
2015-10-13 12:45 ` Jani Nikula
2015-10-13 13:37 ` Daniel Vetter
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