From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA07FC10F11 for ; Wed, 10 Apr 2019 12:54:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 799BE20820 for ; Wed, 10 Apr 2019 12:54:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731614AbfDJMyN convert rfc822-to-8bit (ORCPT ); Wed, 10 Apr 2019 08:54:13 -0400 Received: from mga11.intel.com ([192.55.52.93]:13007 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728553AbfDJMyN (ORCPT ); Wed, 10 Apr 2019 08:54:13 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Apr 2019 05:54:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,332,1549958400"; d="scan'208";a="163043386" Received: from unknown (HELO localhost) ([10.252.46.239]) by fmsmga001.fm.intel.com with ESMTP; 10 Apr 2019 05:54:10 -0700 From: Jani Nikula To: Rodrigo Vivi Cc: intel-gfx@lists.freedesktop.org, Ville =?utf-8?B?U3lyasOkbMOk?= , Manasi Navare , Matt Atwood , "Lee\, Shawn C" , Dave Airlie , stable@vger.kernel.org Subject: Re: [PATCH v2] drm/i915/dp: revert back to max link rate and lane count on eDP In-Reply-To: <20190405172316.GC25637@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20190405072439.8922-1-jani.nikula@intel.com> <20190405075220.9815-1-jani.nikula@intel.com> <20190405172316.GC25637@intel.com> Date: Wed, 10 Apr 2019 15:54:23 +0300 Message-ID: <877ec2hvgg.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8BIT Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org On Fri, 05 Apr 2019, Rodrigo Vivi wrote: > On Fri, Apr 05, 2019 at 10:52:20AM +0300, Jani Nikula wrote: >> Commit 7769db588384 ("drm/i915/dp: optimize eDP 1.4+ link config fast >> and narrow") started to optize the eDP 1.4+ link config, both per spec >> and as preparation for display stream compression support. >> >> Sadly, we again face panels that flat out fail with parameters they >> claim to support. Revert, and go back to the drawing board. >> >> v2: Actually revert to max params instead of just wide-and-slow. >> >> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109959 >> Fixes: 7769db588384 ("drm/i915/dp: optimize eDP 1.4+ link config fast and narrow") >> Cc: Ville Syrjälä >> Cc: Manasi Navare >> Cc: Rodrigo Vivi >> Cc: Matt Atwood >> Cc: "Lee, Shawn C" >> Cc: Dave Airlie >> Cc: intel-gfx@lists.freedesktop.org >> Cc: # v5.0+ >> Signed-off-by: Jani Nikula > > I can hear from here your "I told you so"... Sorry! > > Reviewed-by: Rodrigo Vivi Thanks, pushed, please cherry-pick this for drm-intel-fixes. BR, Jani. > >> --- >> drivers/gpu/drm/i915/intel_dp.c | 69 +++++---------------------------- >> 1 file changed, 10 insertions(+), 59 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c >> index 72c490..dfa770 100644 >> --- a/drivers/gpu/drm/i915/intel_dp.c >> +++ b/drivers/gpu/drm/i915/intel_dp.c >> @@ -1856,42 +1856,6 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, >> return -EINVAL; >> } >> >> -/* Optimize link config in order: max bpp, min lanes, min clock */ >> -static int >> -intel_dp_compute_link_config_fast(struct intel_dp *intel_dp, >> - struct intel_crtc_state *pipe_config, >> - const struct link_config_limits *limits) >> -{ >> - struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; >> - int bpp, clock, lane_count; >> - int mode_rate, link_clock, link_avail; >> - >> - for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) { >> - mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, >> - bpp); >> - >> - for (lane_count = limits->min_lane_count; >> - lane_count <= limits->max_lane_count; >> - lane_count <<= 1) { >> - for (clock = limits->min_clock; clock <= limits->max_clock; clock++) { >> - link_clock = intel_dp->common_rates[clock]; >> - link_avail = intel_dp_max_data_rate(link_clock, >> - lane_count); >> - >> - if (mode_rate <= link_avail) { >> - pipe_config->lane_count = lane_count; >> - pipe_config->pipe_bpp = bpp; >> - pipe_config->port_clock = link_clock; >> - >> - return 0; >> - } >> - } >> - } >> - } >> - >> - return -EINVAL; >> -} >> - >> static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc) >> { >> int i, num_bpc; >> @@ -2028,15 +1992,13 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, >> limits.min_bpp = 6 * 3; >> limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config); >> >> - if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) { >> + if (intel_dp_is_edp(intel_dp)) { >> /* >> * Use the maximum clock and number of lanes the eDP panel >> - * advertizes being capable of. The eDP 1.3 and earlier panels >> - * are generally designed to support only a single clock and >> - * lane configuration, and typically these values correspond to >> - * the native resolution of the panel. With eDP 1.4 rate select >> - * and DSC, this is decreasingly the case, and we need to be >> - * able to select less than maximum link config. >> + * advertizes being capable of. The panels are generally >> + * designed to support only a single clock and lane >> + * configuration, and typically these values correspond to the >> + * native resolution of the panel. >> */ >> limits.min_lane_count = limits.max_lane_count; >> limits.min_clock = limits.max_clock; >> @@ -2050,22 +2012,11 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, >> intel_dp->common_rates[limits.max_clock], >> limits.max_bpp, adjusted_mode->crtc_clock); >> >> - if (intel_dp_is_edp(intel_dp)) >> - /* >> - * Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4 >> - * section A.1: "It is recommended that the minimum number of >> - * lanes be used, using the minimum link rate allowed for that >> - * lane configuration." >> - * >> - * Note that we use the max clock and lane count for eDP 1.3 and >> - * earlier, and fast vs. wide is irrelevant. >> - */ >> - ret = intel_dp_compute_link_config_fast(intel_dp, pipe_config, >> - &limits); >> - else >> - /* Optimize for slow and wide. */ >> - ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, >> - &limits); >> + /* >> + * Optimize for slow and wide. This is the place to add alternative >> + * optimization policy. >> + */ >> + ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits); >> >> /* enable compression if the mode doesn't fit available BW */ >> DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp->force_dsc_en); >> -- >> 2.20.1 >> -- Jani Nikula, Intel Open Source Graphics Center