* [PATCH v4 1/2] drm/i915/dp: BDW cdclk fix for DP audio
@ 2016-11-01 18:47 Dhinakaran Pandiyan
2016-11-01 18:48 ` [PATCH v4 2/2] drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms Dhinakaran Pandiyan
2016-11-01 19:28 ` [PATCH v4 1/2] drm/i915/dp: BDW cdclk fix for DP audio Jani Nikula
0 siblings, 2 replies; 8+ messages in thread
From: Dhinakaran Pandiyan @ 2016-11-01 18:47 UTC (permalink / raw)
To: intel-gfx
Cc: Jani Nikula, ville.syrjala, libin.yang, Dhinakaran Pandiyan,
stable
According to BSpec, cdclk for BDW has to be not less than 432 MHz with DP
audio enabled, port width x4, and link rate HBR2 (5.4 GHz). With cdclk less
than 432 MHz, enabling audio leads to pipe FIFO underruns and displays
cycling on/off.
>From BSpec:
"Display» BDW-SKL» dpr» [Register] DP_TP_CTL [BDW+,EXCLUDE(CHV)]
Workaround : Do not use DisplayPort with CDCLK less than 432 MHz, audio
enabled, port width x4, and link rate HBR2 (5.4 GHz), or else there may
be audio corruption or screen corruption."
Since, some DP configurations (e.g., MST) use port width x4 and HBR2
link rate, let's increase the cdclk to >= 432 MHz to enable audio for those
cases.
v4: Changed commit message
v3: Combine BDW pixel rate adjustments into a function (Jani)
v2: Restrict fix to BDW
Retain the set cdclk across modesets (Ville)
Cc: stable@vger.kernel.org
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++++++++++++++---
1 file changed, 24 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 895b3dc..37483ee 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10261,6 +10261,27 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
bxt_set_cdclk(to_i915(dev), req_cdclk);
}
+static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
+ int pixel_rate)
+{
+ /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
+ if (crtc_state->ips_enabled)
+ pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
+
+ /* BSpec says "Do not use DisplayPort with CDCLK less than
+ * 432 MHz, audio enabled, port width x4, and link rate
+ * HBR2 (5.4 GHz), or else there may be audio corruption or
+ * screen corruption."
+ */
+ if (intel_crtc_has_dp_encoder(crtc_state) &&
+ crtc_state->has_audio &&
+ crtc_state->port_clock >= 540000 &&
+ crtc_state->lane_count == 4)
+ pixel_rate = max(432000, pixel_rate);
+
+ return pixel_rate;
+}
+
/* compute the max rate for new configuration */
static int ilk_max_pixel_rate(struct drm_atomic_state *state)
{
@@ -10286,9 +10307,9 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state)
pixel_rate = ilk_pipe_pixel_rate(crtc_state);
- /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
- if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
- pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
+ if (IS_BROADWELL(dev_priv))
+ pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
+ pixel_rate);
intel_state->min_pixclk[i] = pixel_rate;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v4 2/2] drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms
2016-11-01 18:47 [PATCH v4 1/2] drm/i915/dp: BDW cdclk fix for DP audio Dhinakaran Pandiyan
@ 2016-11-01 18:48 ` Dhinakaran Pandiyan
2016-11-01 19:35 ` Jani Nikula
2016-11-01 19:28 ` [PATCH v4 1/2] drm/i915/dp: BDW cdclk fix for DP audio Jani Nikula
1 sibling, 1 reply; 8+ messages in thread
From: Dhinakaran Pandiyan @ 2016-11-01 18:48 UTC (permalink / raw)
To: intel-gfx
Cc: Jani Nikula, ville.syrjala, libin.yang, Dhinakaran Pandiyan,
stable, Libin Yang
According to BSpec, cdclk for BDW has to be not less than 432 MHz with DP
audio enabled, port width x4, and link rate HBR2 (5.4 GHz). With cdclk less
than 432 MHz, enabling audio leads to pipe FIFO underruns and displays
cycling on/off.
Let's apply this work around to GEN9 platforms too, as it fixes the same
issue.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97907
Cc: stable@vger.kernel.org
Cc: Libin Yang <libin.yang@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 37483ee..c0ae147 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10264,8 +10264,10 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
int pixel_rate)
{
+ struct drm_device *dev = crtc_state->base.crtc->dev;
+
/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
- if (crtc_state->ips_enabled)
+ if (IS_BROADWELL(to_i915(dev)) && crtc_state->ips_enabled)
pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
/* BSpec says "Do not use DisplayPort with CDCLK less than
@@ -10307,7 +10309,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state)
pixel_rate = ilk_pipe_pixel_rate(crtc_state);
- if (IS_BROADWELL(dev_priv))
+ if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
pixel_rate);
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v4 2/2] drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms
2016-11-01 18:48 ` [PATCH v4 2/2] drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms Dhinakaran Pandiyan
@ 2016-11-01 19:35 ` Jani Nikula
2016-11-01 19:42 ` Pandiyan, Dhinakaran
2016-11-02 20:13 ` [PATCH v5 " Dhinakaran Pandiyan
0 siblings, 2 replies; 8+ messages in thread
From: Jani Nikula @ 2016-11-01 19:35 UTC (permalink / raw)
To: Dhinakaran Pandiyan, intel-gfx
Cc: ville.syrjala, libin.yang, Dhinakaran Pandiyan, stable,
Libin Yang
On Tue, 01 Nov 2016, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> wrote:
> According to BSpec, cdclk for BDW has to be not less than 432 MHz with DP
> audio enabled, port width x4, and link rate HBR2 (5.4 GHz). With cdclk less
> than 432 MHz, enabling audio leads to pipe FIFO underruns and displays
> cycling on/off.
>
> Let's apply this work around to GEN9 platforms too, as it fixes the same
> issue.
I'm too tired to read bspec now, but is gen9 really the answer, or just
Skylake?
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97907
> Cc: stable@vger.kernel.org
> Cc: Libin Yang <libin.yang@linux.intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 37483ee..c0ae147 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10264,8 +10264,10 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
> int pixel_rate)
> {
> + struct drm_device *dev = crtc_state->base.crtc->dev;
Nitpick, I guess I'd make that
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
but no big deal.
> +
> /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> - if (crtc_state->ips_enabled)
> + if (IS_BROADWELL(to_i915(dev)) && crtc_state->ips_enabled)
> pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
>
> /* BSpec says "Do not use DisplayPort with CDCLK less than
> @@ -10307,7 +10309,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state)
>
> pixel_rate = ilk_pipe_pixel_rate(crtc_state);
>
> - if (IS_BROADWELL(dev_priv))
> + if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
> pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
> pixel_rate);
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v4 2/2] drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms
2016-11-01 19:35 ` Jani Nikula
@ 2016-11-01 19:42 ` Pandiyan, Dhinakaran
2016-11-01 19:50 ` Jani Nikula
2016-11-02 20:13 ` [PATCH v5 " Dhinakaran Pandiyan
1 sibling, 1 reply; 8+ messages in thread
From: Pandiyan, Dhinakaran @ 2016-11-01 19:42 UTC (permalink / raw)
To: Nikula, Jani
Cc: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org,
Yang, Libin, stable@vger.kernel.org, libin.yang@linux.intel.com
On Tue, 2016-11-01 at 21:35 +0200, Jani Nikula wrote:
> On Tue, 01 Nov 2016, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> wrote:
> > According to BSpec, cdclk for BDW has to be not less than 432 MHz with DP
> > audio enabled, port width x4, and link rate HBR2 (5.4 GHz). With cdclk less
> > than 432 MHz, enabling audio leads to pipe FIFO underruns and displays
> > cycling on/off.
> >
> > Let's apply this work around to GEN9 platforms too, as it fixes the same
> > issue.
>
> I'm too tired to read bspec now, but is gen9 really the answer, or just
> Skylake?
>
>
Gen9, applies to BXT and KBL as well.
-DK
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97907
> > Cc: stable@vger.kernel.org
> > Cc: Libin Yang <libin.yang@linux.intel.com>
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 6 ++++--
> > 1 file changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 37483ee..c0ae147 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -10264,8 +10264,10 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> > static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
> > int pixel_rate)
> > {
> > + struct drm_device *dev = crtc_state->base.crtc->dev;
>
> Nitpick, I guess I'd make that
>
> struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>
> but no big deal.
>
> > +
> > /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> > - if (crtc_state->ips_enabled)
> > + if (IS_BROADWELL(to_i915(dev)) && crtc_state->ips_enabled)
> > pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
> >
> > /* BSpec says "Do not use DisplayPort with CDCLK less than
> > @@ -10307,7 +10309,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state)
> >
> > pixel_rate = ilk_pipe_pixel_rate(crtc_state);
> >
> > - if (IS_BROADWELL(dev_priv))
> > + if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
> > pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
> > pixel_rate);
>
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v4 2/2] drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms
2016-11-01 19:42 ` Pandiyan, Dhinakaran
@ 2016-11-01 19:50 ` Jani Nikula
2016-11-02 20:15 ` [Intel-gfx] " Pandiyan, Dhinakaran
0 siblings, 1 reply; 8+ messages in thread
From: Jani Nikula @ 2016-11-01 19:50 UTC (permalink / raw)
To: Pandiyan, Dhinakaran
Cc: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org,
Yang, Libin, stable@vger.kernel.org, libin.yang@linux.intel.com
On Tue, 01 Nov 2016, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com> wrote:
> On Tue, 2016-11-01 at 21:35 +0200, Jani Nikula wrote:
>> On Tue, 01 Nov 2016, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> wrote:
>> > According to BSpec, cdclk for BDW has to be not less than 432 MHz with DP
>> > audio enabled, port width x4, and link rate HBR2 (5.4 GHz). With cdclk less
>> > than 432 MHz, enabling audio leads to pipe FIFO underruns and displays
>> > cycling on/off.
>> >
>> > Let's apply this work around to GEN9 platforms too, as it fixes the same
>> > issue.
>>
>> I'm too tired to read bspec now, but is gen9 really the answer, or just
>> Skylake?
>>
>>
>
> Gen9, applies to BXT and KBL as well.
I'll take your word for it, and with that,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> -DK
>
>> >
>> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97907
>> > Cc: stable@vger.kernel.org
>> > Cc: Libin Yang <libin.yang@linux.intel.com>
>> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/intel_display.c | 6 ++++--
>> > 1 file changed, 4 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> > index 37483ee..c0ae147 100644
>> > --- a/drivers/gpu/drm/i915/intel_display.c
>> > +++ b/drivers/gpu/drm/i915/intel_display.c
>> > @@ -10264,8 +10264,10 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
>> > static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
>> > int pixel_rate)
>> > {
>> > + struct drm_device *dev = crtc_state->base.crtc->dev;
>>
>> Nitpick, I guess I'd make that
>>
>> struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>>
>> but no big deal.
>>
>> > +
>> > /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
>> > - if (crtc_state->ips_enabled)
>> > + if (IS_BROADWELL(to_i915(dev)) && crtc_state->ips_enabled)
>> > pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
>> >
>> > /* BSpec says "Do not use DisplayPort with CDCLK less than
>> > @@ -10307,7 +10309,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state)
>> >
>> > pixel_rate = ilk_pipe_pixel_rate(crtc_state);
>> >
>> > - if (IS_BROADWELL(dev_priv))
>> > + if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
>> > pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
>> > pixel_rate);
>>
>
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [Intel-gfx] [PATCH v4 2/2] drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms
2016-11-01 19:50 ` Jani Nikula
@ 2016-11-02 20:15 ` Pandiyan, Dhinakaran
0 siblings, 0 replies; 8+ messages in thread
From: Pandiyan, Dhinakaran @ 2016-11-02 20:15 UTC (permalink / raw)
To: Nikula, Jani
Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org,
libin.yang@linux.intel.com
On Tue, 2016-11-01 at 21:50 +0200, Jani Nikula wrote:
> On Tue, 01 Nov 2016, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com> wrote:
> > On Tue, 2016-11-01 at 21:35 +0200, Jani Nikula wrote:
> >> On Tue, 01 Nov 2016, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> wrote:
> >> > According to BSpec, cdclk for BDW has to be not less than 432 MHz with DP
> >> > audio enabled, port width x4, and link rate HBR2 (5.4 GHz). With cdclk less
> >> > than 432 MHz, enabling audio leads to pipe FIFO underruns and displays
> >> > cycling on/off.
> >> >
> >> > Let's apply this work around to GEN9 platforms too, as it fixes the same
> >> > issue.
> >>
> >> I'm too tired to read bspec now, but is gen9 really the answer, or just
> >> Skylake?
> >>
> >>
> >
> > Gen9, applies to BXT and KBL as well.
>
> I'll take your word for it, and with that,
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>
>
Thanks for the review.
> >
> > -DK
> >
> >> >
> >> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97907
> >> > Cc: stable@vger.kernel.org
> >> > Cc: Libin Yang <libin.yang@linux.intel.com>
> >> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> >> > ---
> >> > drivers/gpu/drm/i915/intel_display.c | 6 ++++--
> >> > 1 file changed, 4 insertions(+), 2 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> >> > index 37483ee..c0ae147 100644
> >> > --- a/drivers/gpu/drm/i915/intel_display.c
> >> > +++ b/drivers/gpu/drm/i915/intel_display.c
> >> > @@ -10264,8 +10264,10 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> >> > static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
> >> > int pixel_rate)
> >> > {
> >> > + struct drm_device *dev = crtc_state->base.crtc->dev;
> >>
> >> Nitpick, I guess I'd make that
> >>
> >> struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> >>
> >> but no big deal.
> >>
> >> > +
> >> > /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> >> > - if (crtc_state->ips_enabled)
> >> > + if (IS_BROADWELL(to_i915(dev)) && crtc_state->ips_enabled)
> >> > pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
> >> >
> >> > /* BSpec says "Do not use DisplayPort with CDCLK less than
> >> > @@ -10307,7 +10309,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state)
> >> >
> >> > pixel_rate = ilk_pipe_pixel_rate(crtc_state);
> >> >
> >> > - if (IS_BROADWELL(dev_priv))
> >> > + if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
> >> > pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
> >> > pixel_rate);
> >>
> >
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v5 2/2] drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms
2016-11-01 19:35 ` Jani Nikula
2016-11-01 19:42 ` Pandiyan, Dhinakaran
@ 2016-11-02 20:13 ` Dhinakaran Pandiyan
1 sibling, 0 replies; 8+ messages in thread
From: Dhinakaran Pandiyan @ 2016-11-02 20:13 UTC (permalink / raw)
To: intel-gfx
Cc: Jani Nikula, libin.yang, Dhinakaran Pandiyan, stable, Libin Yang
According to BSpec, cdclk for BDW has to be not less than 432 MHz with DP
audio enabled, port width x4, and link rate HBR2 (5.4 GHz). With cdclk less
than 432 MHz, enabling audio leads to pipe FIFO underruns and displays
cycling on/off.
Let's apply this work around to GEN9 platforms too, as it fixes the same
issue.
v2: Move drm_device to drm_i915_private conversion
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97907
Cc: stable@vger.kernel.org
Cc: Libin Yang <libin.yang@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 37483ee..0d95a2e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10264,8 +10264,10 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
int pixel_rate)
{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+
/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
- if (crtc_state->ips_enabled)
+ if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
/* BSpec says "Do not use DisplayPort with CDCLK less than
@@ -10307,7 +10309,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state)
pixel_rate = ilk_pipe_pixel_rate(crtc_state);
- if (IS_BROADWELL(dev_priv))
+ if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
pixel_rate);
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v4 1/2] drm/i915/dp: BDW cdclk fix for DP audio
2016-11-01 18:47 [PATCH v4 1/2] drm/i915/dp: BDW cdclk fix for DP audio Dhinakaran Pandiyan
2016-11-01 18:48 ` [PATCH v4 2/2] drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms Dhinakaran Pandiyan
@ 2016-11-01 19:28 ` Jani Nikula
1 sibling, 0 replies; 8+ messages in thread
From: Jani Nikula @ 2016-11-01 19:28 UTC (permalink / raw)
To: Dhinakaran Pandiyan, intel-gfx
Cc: ville.syrjala, libin.yang, Dhinakaran Pandiyan, stable
On Tue, 01 Nov 2016, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> wrote:
> According to BSpec, cdclk for BDW has to be not less than 432 MHz with DP
> audio enabled, port width x4, and link rate HBR2 (5.4 GHz). With cdclk less
> than 432 MHz, enabling audio leads to pipe FIFO underruns and displays
> cycling on/off.
>
> From BSpec:
> "Display» BDW-SKL» dpr» [Register] DP_TP_CTL [BDW+,EXCLUDE(CHV)]
> Workaround : Do not use DisplayPort with CDCLK less than 432 MHz, audio
> enabled, port width x4, and link rate HBR2 (5.4 GHz), or else there may
> be audio corruption or screen corruption."
>
> Since, some DP configurations (e.g., MST) use port width x4 and HBR2
> link rate, let's increase the cdclk to >= 432 MHz to enable audio for those
> cases.
>
> v4: Changed commit message
> v3: Combine BDW pixel rate adjustments into a function (Jani)
> v2: Restrict fix to BDW
> Retain the set cdclk across modesets (Ville)
> Cc: stable@vger.kernel.org
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Yup.
> ---
> drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++++++++++++++---
> 1 file changed, 24 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 895b3dc..37483ee 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10261,6 +10261,27 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> bxt_set_cdclk(to_i915(dev), req_cdclk);
> }
>
> +static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
> + int pixel_rate)
> +{
> + /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> + if (crtc_state->ips_enabled)
> + pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
> +
> + /* BSpec says "Do not use DisplayPort with CDCLK less than
> + * 432 MHz, audio enabled, port width x4, and link rate
> + * HBR2 (5.4 GHz), or else there may be audio corruption or
> + * screen corruption."
> + */
> + if (intel_crtc_has_dp_encoder(crtc_state) &&
> + crtc_state->has_audio &&
> + crtc_state->port_clock >= 540000 &&
> + crtc_state->lane_count == 4)
> + pixel_rate = max(432000, pixel_rate);
> +
> + return pixel_rate;
> +}
> +
> /* compute the max rate for new configuration */
> static int ilk_max_pixel_rate(struct drm_atomic_state *state)
> {
> @@ -10286,9 +10307,9 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state)
>
> pixel_rate = ilk_pipe_pixel_rate(crtc_state);
>
> - /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> - if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
> - pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
> + if (IS_BROADWELL(dev_priv))
> + pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
> + pixel_rate);
>
> intel_state->min_pixclk[i] = pixel_rate;
> }
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2016-11-02 20:15 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-11-01 18:47 [PATCH v4 1/2] drm/i915/dp: BDW cdclk fix for DP audio Dhinakaran Pandiyan
2016-11-01 18:48 ` [PATCH v4 2/2] drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms Dhinakaran Pandiyan
2016-11-01 19:35 ` Jani Nikula
2016-11-01 19:42 ` Pandiyan, Dhinakaran
2016-11-01 19:50 ` Jani Nikula
2016-11-02 20:15 ` [Intel-gfx] " Pandiyan, Dhinakaran
2016-11-02 20:13 ` [PATCH v5 " Dhinakaran Pandiyan
2016-11-01 19:28 ` [PATCH v4 1/2] drm/i915/dp: BDW cdclk fix for DP audio Jani Nikula
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