* [PATCH v2] drm/i915/xe2hpd: Identify the memory type for SKUs with GDDR + ECC
@ 2025-03-24 17:22 Lucas De Marchi
2025-03-24 20:02 ` Matt Roper
0 siblings, 1 reply; 6+ messages in thread
From: Lucas De Marchi @ 2025-03-24 17:22 UTC (permalink / raw)
To: intel-xe, intel-gfx, Vivek Kasireddy, Matt Roper, stable,
Lucas De Marchi
From: Vivek Kasireddy <vivek.kasireddy@intel.com>
Some SKUs of Xe2_HPD platforms (such as BMG) have GDDR memory type
with ECC enabled. We need to identify this scenario and add a new
case in xelpdp_get_dram_info() to handle it. In addition, the
derating value needs to be adjusted accordingly to compensate for
the limited bandwidth.
Bspec: 64602
Cc: Matt Roper <matthew.d.roper@intel.com>
Fixes: 3adcf970dc7e ("drm/xe/bmg: Drop force_probe requirement")
Cc: stable@vger.kernel.org
Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
Changes in v2:
- Add a separate sa_info for the ecc case (Lucas)
- Link to v1: https://lore.kernel.org/r/20250214215944.187407-1-vivek.kasireddy@intel.com
---
drivers/gpu/drm/i915/display/intel_bw.c | 12 ++++++++++++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/soc/intel_dram.c | 4 ++++
drivers/gpu/drm/xe/xe_device_types.h | 1 +
4 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index dc7612658a9da..bb81efec08a01 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -250,6 +250,7 @@ static int icl_get_qgv_points(struct intel_display *display,
qi->deinterleave = 4;
break;
case INTEL_DRAM_GDDR:
+ case INTEL_DRAM_GDDR_ECC:
qi->channel_width = 32;
break;
default:
@@ -404,6 +405,12 @@ static const struct intel_sa_info xe2_hpd_sa_info = {
/* Other values not used by simplified algorithm */
};
+static const struct intel_sa_info xe2_hpd_ecc_sa_info = {
+ .derating = 45,
+ .deprogbwlimit = 53,
+ /* Other values not used by simplified algorithm */
+};
+
static const struct intel_sa_info xe3lpd_sa_info = {
.deburst = 32,
.deprogbwlimit = 65, /* GB/s */
@@ -756,11 +763,16 @@ static unsigned int icl_qgv_bw(struct intel_display *display,
void intel_bw_init_hw(struct intel_display *display)
{
+ const struct dram_info *dram_info = &to_i915(display->drm)->dram_info;
+
if (!HAS_DISPLAY(display))
return;
if (DISPLAY_VER(display) >= 30)
tgl_get_bw_info(display, &xe3lpd_sa_info);
+ else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx &&
+ dram_info->type == INTEL_DRAM_GDDR_ECC)
+ xe2_hpd_get_bw_info(display, &xe2_hpd_ecc_sa_info);
else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx)
xe2_hpd_get_bw_info(display, &xe2_hpd_sa_info);
else if (DISPLAY_VER(display) >= 14)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ffc346379cc2c..54538b6f85df5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -305,6 +305,7 @@ struct drm_i915_private {
INTEL_DRAM_DDR5,
INTEL_DRAM_LPDDR5,
INTEL_DRAM_GDDR,
+ INTEL_DRAM_GDDR_ECC,
} type;
u8 num_qgv_points;
u8 num_psf_gv_points;
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
index 9e310f4099f42..f60eedb0e92cf 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -687,6 +687,10 @@ static int xelpdp_get_dram_info(struct drm_i915_private *i915)
drm_WARN_ON(&i915->drm, !IS_DGFX(i915));
dram_info->type = INTEL_DRAM_GDDR;
break;
+ case 9:
+ drm_WARN_ON(&i915->drm, !IS_DGFX(i915));
+ dram_info->type = INTEL_DRAM_GDDR_ECC;
+ break;
default:
MISSING_CASE(val);
return -EINVAL;
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 1334174388afe..20239d6a2e985 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -587,6 +587,7 @@ struct xe_device {
INTEL_DRAM_DDR5,
INTEL_DRAM_LPDDR5,
INTEL_DRAM_GDDR,
+ INTEL_DRAM_GDDR_ECC,
} type;
u8 num_qgv_points;
u8 num_psf_gv_points;
---
base-commit: 74f632d1bd3b90ed79883361ca25f1225c0aee58
change-id: 20250321-tip-23d2af2e3291
Best regards,
--
Lucas De Marchi <lucas.demarchi@intel.com>
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2] drm/i915/xe2hpd: Identify the memory type for SKUs with GDDR + ECC
2025-03-24 17:22 [PATCH v2] drm/i915/xe2hpd: Identify the memory type for SKUs with GDDR + ECC Lucas De Marchi
@ 2025-03-24 20:02 ` Matt Roper
2025-03-25 1:17 ` Lucas De Marchi
0 siblings, 1 reply; 6+ messages in thread
From: Matt Roper @ 2025-03-24 20:02 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe, intel-gfx, Vivek Kasireddy, stable
On Mon, Mar 24, 2025 at 10:22:33AM -0700, Lucas De Marchi wrote:
> From: Vivek Kasireddy <vivek.kasireddy@intel.com>
>
> Some SKUs of Xe2_HPD platforms (such as BMG) have GDDR memory type
> with ECC enabled. We need to identify this scenario and add a new
> case in xelpdp_get_dram_info() to handle it. In addition, the
> derating value needs to be adjusted accordingly to compensate for
> the limited bandwidth.
>
> Bspec: 64602
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Fixes: 3adcf970dc7e ("drm/xe/bmg: Drop force_probe requirement")
> Cc: stable@vger.kernel.org
> Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> Changes in v2:
> - Add a separate sa_info for the ecc case (Lucas)
> - Link to v1: https://lore.kernel.org/r/20250214215944.187407-1-vivek.kasireddy@intel.com
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 12 ++++++++++++
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/soc/intel_dram.c | 4 ++++
> drivers/gpu/drm/xe/xe_device_types.h | 1 +
> 4 files changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index dc7612658a9da..bb81efec08a01 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -250,6 +250,7 @@ static int icl_get_qgv_points(struct intel_display *display,
> qi->deinterleave = 4;
> break;
> case INTEL_DRAM_GDDR:
> + case INTEL_DRAM_GDDR_ECC:
> qi->channel_width = 32;
> break;
> default:
> @@ -404,6 +405,12 @@ static const struct intel_sa_info xe2_hpd_sa_info = {
> /* Other values not used by simplified algorithm */
> };
>
> +static const struct intel_sa_info xe2_hpd_ecc_sa_info = {
> + .derating = 45,
> + .deprogbwlimit = 53,
> + /* Other values not used by simplified algorithm */
> +};
> +
> static const struct intel_sa_info xe3lpd_sa_info = {
> .deburst = 32,
> .deprogbwlimit = 65, /* GB/s */
> @@ -756,11 +763,16 @@ static unsigned int icl_qgv_bw(struct intel_display *display,
>
> void intel_bw_init_hw(struct intel_display *display)
> {
> + const struct dram_info *dram_info = &to_i915(display->drm)->dram_info;
> +
> if (!HAS_DISPLAY(display))
> return;
>
> if (DISPLAY_VER(display) >= 30)
> tgl_get_bw_info(display, &xe3lpd_sa_info);
> + else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx &&
> + dram_info->type == INTEL_DRAM_GDDR_ECC)
> + xe2_hpd_get_bw_info(display, &xe2_hpd_ecc_sa_info);
> else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx)
> xe2_hpd_get_bw_info(display, &xe2_hpd_sa_info);
> else if (DISPLAY_VER(display) >= 14)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index ffc346379cc2c..54538b6f85df5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -305,6 +305,7 @@ struct drm_i915_private {
> INTEL_DRAM_DDR5,
> INTEL_DRAM_LPDDR5,
> INTEL_DRAM_GDDR,
> + INTEL_DRAM_GDDR_ECC,
> } type;
> u8 num_qgv_points;
> u8 num_psf_gv_points;
> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
> index 9e310f4099f42..f60eedb0e92cf 100644
> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
> @@ -687,6 +687,10 @@ static int xelpdp_get_dram_info(struct drm_i915_private *i915)
> drm_WARN_ON(&i915->drm, !IS_DGFX(i915));
> dram_info->type = INTEL_DRAM_GDDR;
> break;
> + case 9:
> + drm_WARN_ON(&i915->drm, !IS_DGFX(i915));
> + dram_info->type = INTEL_DRAM_GDDR_ECC;
> + break;
> default:
> MISSING_CASE(val);
> return -EINVAL;
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 1334174388afe..20239d6a2e985 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -587,6 +587,7 @@ struct xe_device {
> INTEL_DRAM_DDR5,
> INTEL_DRAM_LPDDR5,
> INTEL_DRAM_GDDR,
> + INTEL_DRAM_GDDR_ECC,
> } type;
> u8 num_qgv_points;
> u8 num_psf_gv_points;
>
> ---
> base-commit: 74f632d1bd3b90ed79883361ca25f1225c0aee58
> change-id: 20250321-tip-23d2af2e3291
>
> Best regards,
> --
> Lucas De Marchi <lucas.demarchi@intel.com>
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] drm/i915/xe2hpd: Identify the memory type for SKUs with GDDR + ECC
2025-03-24 20:02 ` Matt Roper
@ 2025-03-25 1:17 ` Lucas De Marchi
2025-03-25 9:03 ` Jani Nikula
0 siblings, 1 reply; 6+ messages in thread
From: Lucas De Marchi @ 2025-03-25 1:17 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe, intel-gfx, Vivek Kasireddy, stable
On Mon, Mar 24, 2025 at 01:02:07PM -0700, Matt Roper wrote:
>On Mon, Mar 24, 2025 at 10:22:33AM -0700, Lucas De Marchi wrote:
>> From: Vivek Kasireddy <vivek.kasireddy@intel.com>
>>
>> Some SKUs of Xe2_HPD platforms (such as BMG) have GDDR memory type
>> with ECC enabled. We need to identify this scenario and add a new
>> case in xelpdp_get_dram_info() to handle it. In addition, the
>> derating value needs to be adjusted accordingly to compensate for
>> the limited bandwidth.
>>
>> Bspec: 64602
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Fixes: 3adcf970dc7e ("drm/xe/bmg: Drop force_probe requirement")
>> Cc: stable@vger.kernel.org
>> Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Thanks. Patch pushed to drm-intel-next.
Lucas De Marchi
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] drm/i915/xe2hpd: Identify the memory type for SKUs with GDDR + ECC
2025-03-25 1:17 ` Lucas De Marchi
@ 2025-03-25 9:03 ` Jani Nikula
2025-03-25 14:52 ` Lucas De Marchi
0 siblings, 1 reply; 6+ messages in thread
From: Jani Nikula @ 2025-03-25 9:03 UTC (permalink / raw)
To: Lucas De Marchi, Matt Roper; +Cc: intel-xe, intel-gfx, Vivek Kasireddy, stable
On Mon, 24 Mar 2025, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> On Mon, Mar 24, 2025 at 01:02:07PM -0700, Matt Roper wrote:
>>On Mon, Mar 24, 2025 at 10:22:33AM -0700, Lucas De Marchi wrote:
>>> From: Vivek Kasireddy <vivek.kasireddy@intel.com>
>>>
>>> Some SKUs of Xe2_HPD platforms (such as BMG) have GDDR memory type
>>> with ECC enabled. We need to identify this scenario and add a new
>>> case in xelpdp_get_dram_info() to handle it. In addition, the
>>> derating value needs to be adjusted accordingly to compensate for
>>> the limited bandwidth.
>>>
>>> Bspec: 64602
>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>> Fixes: 3adcf970dc7e ("drm/xe/bmg: Drop force_probe requirement")
>>> Cc: stable@vger.kernel.org
FYI, this does not cherry-pick cleanly to drm-intel-next-fixes, and
needs a backport.
There are dependencies on at least
4051c59e2a6a ("drm/i915/xe3lpd: Update bandwidth parameters")
9377c00cfdb5 ("drm/i915/display: Convert intel_bw.c internally to intel_display")
d706998b6da6 ("drm/i915/display: Convert intel_bw.c externally to intel_display")
but I don't think we want to backport those.
BR,
Jani.
>>> Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com>
>>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>
>>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
> Thanks. Patch pushed to drm-intel-next.
>
> Lucas De Marchi
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] drm/i915/xe2hpd: Identify the memory type for SKUs with GDDR + ECC
2025-03-25 9:03 ` Jani Nikula
@ 2025-03-25 14:52 ` Lucas De Marchi
2025-04-09 12:42 ` Jani Nikula
0 siblings, 1 reply; 6+ messages in thread
From: Lucas De Marchi @ 2025-03-25 14:52 UTC (permalink / raw)
To: Jani Nikula; +Cc: Matt Roper, intel-xe, intel-gfx, Vivek Kasireddy, stable
On Tue, Mar 25, 2025 at 11:03:13AM +0200, Jani Nikula wrote:
>On Mon, 24 Mar 2025, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>> On Mon, Mar 24, 2025 at 01:02:07PM -0700, Matt Roper wrote:
>>>On Mon, Mar 24, 2025 at 10:22:33AM -0700, Lucas De Marchi wrote:
>>>> From: Vivek Kasireddy <vivek.kasireddy@intel.com>
>>>>
>>>> Some SKUs of Xe2_HPD platforms (such as BMG) have GDDR memory type
>>>> with ECC enabled. We need to identify this scenario and add a new
>>>> case in xelpdp_get_dram_info() to handle it. In addition, the
>>>> derating value needs to be adjusted accordingly to compensate for
>>>> the limited bandwidth.
>>>>
>>>> Bspec: 64602
>>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>>> Fixes: 3adcf970dc7e ("drm/xe/bmg: Drop force_probe requirement")
>>>> Cc: stable@vger.kernel.org
>
>FYI, this does not cherry-pick cleanly to drm-intel-next-fixes, and
>needs a backport.
>
>There are dependencies on at least
>
>4051c59e2a6a ("drm/i915/xe3lpd: Update bandwidth parameters")
>9377c00cfdb5 ("drm/i915/display: Convert intel_bw.c internally to intel_display")
>d706998b6da6 ("drm/i915/display: Convert intel_bw.c externally to intel_display")
>
>but I don't think we want to backport those.
yeah, I expected issues like that and was going to provide the specific
patch for stable. However I thought it would at least apply to
drm-intel-next-fixes :(. Below is the patch to drm-intel-next-fixes. It
also applies cleanly to 6.13. For 6.12 there's an additional small
conflict due to the DISPLAY_VER_FULL conversion.
Also available at https://gitlab.freedesktop.org/demarchi/xe/-/commit/14cb226dc4526971fb7cfd1e79bb3196734f2ab4
Thanks
Lucas De Marchi
-------
From f61fd762498be6291626cb9cfcb8da28be6485e3 Mon Sep 17 00:00:00 2001
From: Vivek Kasireddy <vivek.kasireddy@intel.com>
Date: Mon, 24 Mar 2025 10:22:33 -0700
Subject: [PATCH] drm/i915/xe2hpd: Identify the memory type for SKUs with GDDR
+ ECC
Some SKUs of Xe2_HPD platforms (such as BMG) have GDDR memory type
with ECC enabled. We need to identify this scenario and add a new
case in xelpdp_get_dram_info() to handle it. In addition, the
derating value needs to be adjusted accordingly to compensate for
the limited bandwidth.
Bspec: 64602
Cc: Matt Roper <matthew.d.roper@intel.com>
Fixes: 3adcf970dc7e ("drm/xe/bmg: Drop force_probe requirement")
Cc: stable@vger.kernel.org
Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250324-tip-v2-1-38397de319f8@intel.com
(cherry picked from commit 327e30123cafcb45c0fc5843da0367b90332999d)
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 14 +++++++++++++-
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/soc/intel_dram.c | 4 ++++
drivers/gpu/drm/xe/xe_device_types.h | 1 +
4 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 048be28722477..5e49f8f7c9804 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -244,6 +244,7 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
qi->deinterleave = 4;
break;
case INTEL_DRAM_GDDR:
+ case INTEL_DRAM_GDDR_ECC:
qi->channel_width = 32;
break;
default:
@@ -398,6 +399,12 @@ static const struct intel_sa_info xe2_hpd_sa_info = {
/* Other values not used by simplified algorithm */
};
+static const struct intel_sa_info xe2_hpd_ecc_sa_info = {
+ .derating = 45,
+ .deprogbwlimit = 53,
+ /* Other values not used by simplified algorithm */
+};
+
static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
{
struct intel_qgv_info qi = {};
@@ -740,10 +747,15 @@ static unsigned int icl_qgv_bw(struct drm_i915_private *i915,
void intel_bw_init_hw(struct drm_i915_private *dev_priv)
{
+ const struct dram_info *dram_info = &dev_priv->dram_info;
+
if (!HAS_DISPLAY(dev_priv))
return;
- if (DISPLAY_VERx100(dev_priv) >= 1401 && IS_DGFX(dev_priv))
+ if (DISPLAY_VERx100(dev_priv) >= 1401 && IS_DGFX(dev_priv) &&
+ dram_info->type == INTEL_DRAM_GDDR_ECC)
+ xe2_hpd_get_bw_info(dev_priv, &xe2_hpd_ecc_sa_info);
+ else if (DISPLAY_VERx100(dev_priv) >= 1401 && IS_DGFX(dev_priv))
xe2_hpd_get_bw_info(dev_priv, &xe2_hpd_sa_info);
else if (DISPLAY_VER(dev_priv) >= 14)
tgl_get_bw_info(dev_priv, &mtl_sa_info);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ffc346379cc2c..54538b6f85df5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -305,6 +305,7 @@ struct drm_i915_private {
INTEL_DRAM_DDR5,
INTEL_DRAM_LPDDR5,
INTEL_DRAM_GDDR,
+ INTEL_DRAM_GDDR_ECC,
} type;
u8 num_qgv_points;
u8 num_psf_gv_points;
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
index 9e310f4099f42..f60eedb0e92cf 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -687,6 +687,10 @@ static int xelpdp_get_dram_info(struct drm_i915_private *i915)
drm_WARN_ON(&i915->drm, !IS_DGFX(i915));
dram_info->type = INTEL_DRAM_GDDR;
break;
+ case 9:
+ drm_WARN_ON(&i915->drm, !IS_DGFX(i915));
+ dram_info->type = INTEL_DRAM_GDDR_ECC;
+ break;
default:
MISSING_CASE(val);
return -EINVAL;
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 72ef0b6fc4250..9f8667ebba853 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -585,6 +585,7 @@ struct xe_device {
INTEL_DRAM_DDR5,
INTEL_DRAM_LPDDR5,
INTEL_DRAM_GDDR,
+ INTEL_DRAM_GDDR_ECC,
} type;
u8 num_qgv_points;
u8 num_psf_gv_points;
--
2.49.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2] drm/i915/xe2hpd: Identify the memory type for SKUs with GDDR + ECC
2025-03-25 14:52 ` Lucas De Marchi
@ 2025-04-09 12:42 ` Jani Nikula
0 siblings, 0 replies; 6+ messages in thread
From: Jani Nikula @ 2025-04-09 12:42 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: Matt Roper, intel-xe, intel-gfx, Vivek Kasireddy, stable
On Tue, 25 Mar 2025, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> On Tue, Mar 25, 2025 at 11:03:13AM +0200, Jani Nikula wrote:
>>On Mon, 24 Mar 2025, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>>> On Mon, Mar 24, 2025 at 01:02:07PM -0700, Matt Roper wrote:
>>>>On Mon, Mar 24, 2025 at 10:22:33AM -0700, Lucas De Marchi wrote:
>>>>> From: Vivek Kasireddy <vivek.kasireddy@intel.com>
>>>>>
>>>>> Some SKUs of Xe2_HPD platforms (such as BMG) have GDDR memory type
>>>>> with ECC enabled. We need to identify this scenario and add a new
>>>>> case in xelpdp_get_dram_info() to handle it. In addition, the
>>>>> derating value needs to be adjusted accordingly to compensate for
>>>>> the limited bandwidth.
>>>>>
>>>>> Bspec: 64602
>>>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>>>> Fixes: 3adcf970dc7e ("drm/xe/bmg: Drop force_probe requirement")
>>>>> Cc: stable@vger.kernel.org
>>
>>FYI, this does not cherry-pick cleanly to drm-intel-next-fixes, and
>>needs a backport.
>>
>>There are dependencies on at least
>>
>>4051c59e2a6a ("drm/i915/xe3lpd: Update bandwidth parameters")
>>9377c00cfdb5 ("drm/i915/display: Convert intel_bw.c internally to intel_display")
>>d706998b6da6 ("drm/i915/display: Convert intel_bw.c externally to intel_display")
>>
>>but I don't think we want to backport those.
>
> yeah, I expected issues like that and was going to provide the specific
> patch for stable. However I thought it would at least apply to
> drm-intel-next-fixes :(. Below is the patch to drm-intel-next-fixes. It
> also applies cleanly to 6.13. For 6.12 there's an additional small
> conflict due to the DISPLAY_VER_FULL conversion.
Thanks, just sent a fixes pull request with this.
BR,
Jani.
>
> Also available at https://gitlab.freedesktop.org/demarchi/xe/-/commit/14cb226dc4526971fb7cfd1e79bb3196734f2ab4
>
> Thanks
> Lucas De Marchi
> -------
>
> From f61fd762498be6291626cb9cfcb8da28be6485e3 Mon Sep 17 00:00:00 2001
> From: Vivek Kasireddy <vivek.kasireddy@intel.com>
> Date: Mon, 24 Mar 2025 10:22:33 -0700
> Subject: [PATCH] drm/i915/xe2hpd: Identify the memory type for SKUs with GDDR
> + ECC
>
> Some SKUs of Xe2_HPD platforms (such as BMG) have GDDR memory type
> with ECC enabled. We need to identify this scenario and add a new
> case in xelpdp_get_dram_info() to handle it. In addition, the
> derating value needs to be adjusted accordingly to compensate for
> the limited bandwidth.
>
> Bspec: 64602
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Fixes: 3adcf970dc7e ("drm/xe/bmg: Drop force_probe requirement")
> Cc: stable@vger.kernel.org
> Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> Acked-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Link: https://patchwork.freedesktop.org/patch/msgid/20250324-tip-v2-1-38397de319f8@intel.com
> (cherry picked from commit 327e30123cafcb45c0fc5843da0367b90332999d)
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 14 +++++++++++++-
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/soc/intel_dram.c | 4 ++++
> drivers/gpu/drm/xe/xe_device_types.h | 1 +
> 4 files changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 048be28722477..5e49f8f7c9804 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -244,6 +244,7 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
> qi->deinterleave = 4;
> break;
> case INTEL_DRAM_GDDR:
> + case INTEL_DRAM_GDDR_ECC:
> qi->channel_width = 32;
> break;
> default:
> @@ -398,6 +399,12 @@ static const struct intel_sa_info xe2_hpd_sa_info = {
> /* Other values not used by simplified algorithm */
> };
>
> +static const struct intel_sa_info xe2_hpd_ecc_sa_info = {
> + .derating = 45,
> + .deprogbwlimit = 53,
> + /* Other values not used by simplified algorithm */
> +};
> +
> static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
> {
> struct intel_qgv_info qi = {};
> @@ -740,10 +747,15 @@ static unsigned int icl_qgv_bw(struct drm_i915_private *i915,
>
> void intel_bw_init_hw(struct drm_i915_private *dev_priv)
> {
> + const struct dram_info *dram_info = &dev_priv->dram_info;
> +
> if (!HAS_DISPLAY(dev_priv))
> return;
>
> - if (DISPLAY_VERx100(dev_priv) >= 1401 && IS_DGFX(dev_priv))
> + if (DISPLAY_VERx100(dev_priv) >= 1401 && IS_DGFX(dev_priv) &&
> + dram_info->type == INTEL_DRAM_GDDR_ECC)
> + xe2_hpd_get_bw_info(dev_priv, &xe2_hpd_ecc_sa_info);
> + else if (DISPLAY_VERx100(dev_priv) >= 1401 && IS_DGFX(dev_priv))
> xe2_hpd_get_bw_info(dev_priv, &xe2_hpd_sa_info);
> else if (DISPLAY_VER(dev_priv) >= 14)
> tgl_get_bw_info(dev_priv, &mtl_sa_info);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index ffc346379cc2c..54538b6f85df5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -305,6 +305,7 @@ struct drm_i915_private {
> INTEL_DRAM_DDR5,
> INTEL_DRAM_LPDDR5,
> INTEL_DRAM_GDDR,
> + INTEL_DRAM_GDDR_ECC,
> } type;
> u8 num_qgv_points;
> u8 num_psf_gv_points;
> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
> index 9e310f4099f42..f60eedb0e92cf 100644
> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
> @@ -687,6 +687,10 @@ static int xelpdp_get_dram_info(struct drm_i915_private *i915)
> drm_WARN_ON(&i915->drm, !IS_DGFX(i915));
> dram_info->type = INTEL_DRAM_GDDR;
> break;
> + case 9:
> + drm_WARN_ON(&i915->drm, !IS_DGFX(i915));
> + dram_info->type = INTEL_DRAM_GDDR_ECC;
> + break;
> default:
> MISSING_CASE(val);
> return -EINVAL;
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 72ef0b6fc4250..9f8667ebba853 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -585,6 +585,7 @@ struct xe_device {
> INTEL_DRAM_DDR5,
> INTEL_DRAM_LPDDR5,
> INTEL_DRAM_GDDR,
> + INTEL_DRAM_GDDR_ECC,
> } type;
> u8 num_qgv_points;
> u8 num_psf_gv_points;
--
Jani Nikula, Intel
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2025-03-24 17:22 [PATCH v2] drm/i915/xe2hpd: Identify the memory type for SKUs with GDDR + ECC Lucas De Marchi
2025-03-24 20:02 ` Matt Roper
2025-03-25 1:17 ` Lucas De Marchi
2025-03-25 9:03 ` Jani Nikula
2025-03-25 14:52 ` Lucas De Marchi
2025-04-09 12:42 ` Jani Nikula
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