From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B18450276; Sat, 7 Feb 2026 21:23:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770499383; cv=none; b=TplnvZm4QuOec6CLBjUGqOrrFxAiSaGSSQrIs8oLiu6DB/qWaCGwF3mixhxni148jouYfCBXSS3m2/jLcdUaCJwvncqVUo+aUqXPPTgD4Gp3GMytQwmHOPQWHgx3/HZjIgPqkF4iURsOYYZ7R8qVNLQtyuYNqJhkWgph5G9rDXU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770499383; c=relaxed/simple; bh=WbQjMhOPtfr910QnshnlTPVJ9QLKcXL9+3iN1npfDkY=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=GGQSwZ5ZwmVJQI76/ypI8ZuI97gwGCUxaj2WgzecFL+PBvrrH62TT5gaWWNViuXWjxx54ncgP/G+/JU9zzZK1KLo+BFx0WbMm7JibGNL7U0fG39PEN33h79nl2rArspqa7q3qp0iwtpkuxP2ESnNzIzHL+aaZHFNhBnR0DzZ7S0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=U4sh1Dr+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="U4sh1Dr+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 48C30C116D0; Sat, 7 Feb 2026 21:23:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770499383; bh=WbQjMhOPtfr910QnshnlTPVJ9QLKcXL9+3iN1npfDkY=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=U4sh1Dr+33+z2Az4uQQxZlCV185e+HSGN69pUjK+oAu6xX5lSpfOqk2Uk1JbEYue6 xoRKzNQ49/AilbKlwUrgxnogdzN+HHNwgGIW1x+nNdCKGCapzLXO/Vb8gWZY4YEpaL sBiVXDZxRTJ1GNZwaxvwWAbHe4j6sdl+YE6uxqYmE+gN5y5FamH5cklisvr3PGkgVq GtB0ILwj09xwIn4nZEXm+3X2z3HjwX2KbAoIYbWb6EvmedV1t7uaX/A3Np3bUUVDPA oBhylSMw7KGelu550GrblwHyOP+nyPcvMFFMnYnn+8Y1zNogvRzVL1w/LUIXTJl6tF 8f6NcP1140CzQ== From: Thomas Gleixner To: Marc Zyngier , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Robin Murphy , stable@vger.kernel.org Subject: Re: [PATCH] irqchip/gic-v3-its: Limit number of per-device MSIs to the range the ITS supports In-Reply-To: <20260206154816.3582887-1-maz@kernel.org> References: <20260206154816.3582887-1-maz@kernel.org> Date: Sat, 07 Feb 2026 22:22:56 +0100 Message-ID: <87h5rsb64v.ffs@tglx> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Fri, Feb 06 2026 at 15:48, Marc Zyngier wrote: > The ITS driver blindly assumes that EventIDs are in abundant supply, > to the point where it never checks how many the HW actually supports. > > It turns out that some pretty esoteric integrations make it so that > only a few bits are available, all the way down to a. single. bit. > > Enforce the advertised limitation at the point of allocating the > device structure, and hope that the endpoint driver can deal with > such limitation. > > Signed-off-by: Marc Zyngier > Cc: stable@vger.kernel.org Can you please provide a Fixes tag? Thanks, tglx