[PATCH 01/15] drm/i915: Check pipe source size when using skl+ scalers

[PATCH 01/15] drm/i915: Check pipe source size when using skl+ scalers

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The skl+ scalers only sample 12 bits of PIPESRC so we can't
do any plane scaling at all when the pipe source size is >4k.

Make sure the pipe source size is also below the scaler's src
size limits. Might not be 100% accurate, but should at least be
safe. We can refine the limits later if we discover that recent
hw is less restricted.

Cc: stable@vger.kernel.org
Tested-by: Ross Zwisler <zwisler@google.com>
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8357
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/skl_scaler.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index 473d53610b92..0e7e014fcc71 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -111,6 +111,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
+	int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
+	int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
 	int min_src_w, min_src_h, min_dst_w, min_dst_h;
 	int max_src_w, max_src_h, max_dst_w, max_dst_h;
 
@@ -207,6 +209,21 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
 		return -EINVAL;
 	}
 
+	/*
+	 * The pipe scaler does not use all the bits of PIPESRC, at least
+	 * on the earlier platforms. So even when we're scaling a plane
+	 * the *pipe* source size must not be too large. For simplicity
+	 * we assume the limits match the scaler source size limits. Might
+	 * not be 100% accurate on all platforms, but good enough for now.
+	 */
+	if (pipe_src_w > max_src_w || pipe_src_h > max_src_h) {
+		drm_dbg_kms(&dev_priv->drm,
+			    "scaler_user index %u.%u: pipe src size %ux%u "
+			    "is out of scaler range\n",
+			    crtc->pipe, scaler_user, pipe_src_w, pipe_src_h);
+		return -EINVAL;
+	}
+
 	/* mark this plane as a scaler user in crtc_state */
 	scaler_state->scaler_users |= (1 << scaler_user);
 	drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "
-- 
2.39.2

Re: [Intel-gfx] [PATCH 01/15] drm/i915: Check pipe source size when using skl+ scalers

[Jani Nikula]

On Tue, 18 Apr 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The skl+ scalers only sample 12 bits of PIPESRC so we can't
> do any plane scaling at all when the pipe source size is >4k.
>
> Make sure the pipe source size is also below the scaler's src
> size limits. Might not be 100% accurate, but should at least be
> safe. We can refine the limits later if we discover that recent
> hw is less restricted.
>
> Cc: stable@vger.kernel.org
> Tested-by: Ross Zwisler <zwisler@google.com>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8357
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/skl_scaler.c | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
> index 473d53610b92..0e7e014fcc71 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> @@ -111,6 +111,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	const struct drm_display_mode *adjusted_mode =
>  		&crtc_state->hw.adjusted_mode;
> +	int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
> +	int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
>  	int min_src_w, min_src_h, min_dst_w, min_dst_h;
>  	int max_src_w, max_src_h, max_dst_w, max_dst_h;
>  
> @@ -207,6 +209,21 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
>  		return -EINVAL;
>  	}
>  
> +	/*
> +	 * The pipe scaler does not use all the bits of PIPESRC, at least
> +	 * on the earlier platforms. So even when we're scaling a plane
> +	 * the *pipe* source size must not be too large. For simplicity
> +	 * we assume the limits match the scaler source size limits. Might
> +	 * not be 100% accurate on all platforms, but good enough for now.
> +	 */
> +	if (pipe_src_w > max_src_w || pipe_src_h > max_src_h) {
> +		drm_dbg_kms(&dev_priv->drm,
> +			    "scaler_user index %u.%u: pipe src size %ux%u "
> +			    "is out of scaler range\n",
> +			    crtc->pipe, scaler_user, pipe_src_w, pipe_src_h);
> +		return -EINVAL;
> +	}
> +
>  	/* mark this plane as a scaler user in crtc_state */
>  	scaler_state->scaler_users |= (1 << scaler_user);
>  	drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "

-- 
Jani Nikula, Intel Open Source Graphics Center