[PATCH for 7.0 0/2] ALSA/SOF Intel: Enforce stricter period size for NVL

[PATCH for 7.0 0/2] ALSA/SOF Intel: Enforce stricter period size for NVL

[Peter Ujfalusi]

Hi,

NVL and NVL-S (ACE4) needs to use stricter period size constraint to
meet the address alignment for each BDLE buffer (start of each period in
the continuous ALSA buffer) set in the HDA specification.

It would be great if these can be sent for 7.0 as last minute if it is
doable, I left out the Fixes tag from the first patch as that is
introduced in 7.0.

Regards
Peter
---
Kai Vehmanen (2):
  ALSA: hda/intel: enforce stricter period-size alignment for Intel NVL
  ASoC: SOF: Intel: hda: modify period size constraints for ACE4

 sound/hda/controllers/intel.c |  7 +++++--
 sound/soc/sof/intel/hda-pcm.c | 14 ++++++++++++--
 2 files changed, 17 insertions(+), 4 deletions(-)

-- 
2.53.0

[PATCH for 7.0 1/2] ALSA: hda/intel: enforce stricter period-size alignment for Intel NVL

[Peter Ujfalusi]

From: Kai Vehmanen <kai.vehmanen@linux.intel.com>

Intel ACE4 based products set more strict constraints on HDA BDLE start
address and length alignment. Modify capability flags to drop
AZX_DCAPS_NO_ALIGN_BUFSIZE for Intel Nova Lake platforms.

Fixes: 7f428282fde3 ("ALSA: hda: controllers: intel: add support for Nova Lake")
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Liam Girdwood <liam.r.girdwood@intel.com>
---
 sound/hda/controllers/intel.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/sound/hda/controllers/intel.c b/sound/hda/controllers/intel.c
index 1b22dbf7a719..257c498c3260 100644
--- a/sound/hda/controllers/intel.c
+++ b/sound/hda/controllers/intel.c
@@ -295,6 +295,9 @@ enum {
 #define AZX_DCAPS_INTEL_LNL \
 	(AZX_DCAPS_INTEL_SKYLAKE | AZX_DCAPS_PIO_COMMANDS)
 
+#define AZX_DCAPS_INTEL_NVL \
+	(AZX_DCAPS_INTEL_LNL & ~AZX_DCAPS_NO_ALIGN_BUFSIZE)
+
 /* quirks for ATI SB / AMD Hudson */
 #define AZX_DCAPS_PRESET_ATI_SB \
 	(AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\
@@ -2552,8 +2555,8 @@ static const struct pci_device_id azx_ids[] = {
 	/* Wildcat Lake */
 	{ PCI_DEVICE_DATA(INTEL, HDA_WCL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) },
 	/* Nova Lake */
-	{ PCI_DEVICE_DATA(INTEL, HDA_NVL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) },
-	{ PCI_DEVICE_DATA(INTEL, HDA_NVL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) },
+	{ PCI_DEVICE_DATA(INTEL, HDA_NVL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_NVL) },
+	{ PCI_DEVICE_DATA(INTEL, HDA_NVL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_NVL) },
 	/* Apollolake (Broxton-P) */
 	{ PCI_DEVICE_DATA(INTEL, HDA_APL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) },
 	/* Gemini-Lake */
-- 
2.53.0

[PATCH for 7.0 2/2] ASoC: SOF: Intel: hda: modify period size constraints for ACE4

[Peter Ujfalusi]

From: Kai Vehmanen <kai.vehmanen@linux.intel.com>

Intel ACE4 based products set more strict constraints on HDA BDLE start
address and length alignment. Add a constraint to align period size to
128 bytes.

The commit removes the "minimum as per HDA spec" comment. This comment
was misleading as spec actually does allow a 2 byte BDLE length, and
more importantly, period size also directly impacts how the BDLE start
addresses are aligned, so it is not sufficient just to consider allowed
buffer length.

Fixes: d3df422f66e8 ("ASoC: SOF: Intel: add initial support for NVL-S")
Cc: stable@vger.kernel.org
Reported-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Liam Girdwood <liam.r.girdwood@intel.com>
---
 sound/soc/sof/intel/hda-pcm.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/sound/soc/sof/intel/hda-pcm.c b/sound/soc/sof/intel/hda-pcm.c
index da6c1e7263cd..16a364072821 100644
--- a/sound/soc/sof/intel/hda-pcm.c
+++ b/sound/soc/sof/intel/hda-pcm.c
@@ -219,6 +219,7 @@ EXPORT_SYMBOL_NS(hda_dsp_pcm_pointer, "SND_SOC_SOF_INTEL_HDA_COMMON");
 int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
 		     struct snd_pcm_substream *substream)
 {
+	const struct sof_intel_dsp_desc *chip_info = get_chip_info(sdev->pdata);
 	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
 	struct snd_pcm_runtime *runtime = substream->runtime;
 	struct snd_soc_component *scomp = sdev->component;
@@ -268,8 +269,17 @@ int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
 		return -ENODEV;
 	}
 
-	/* minimum as per HDA spec */
-	snd_pcm_hw_constraint_step(substream->runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 4);
+	/*
+	 * Set period size constraint to ensure BDLE buffer length and
+	 * start address alignment requirements are met. Align to 128
+	 * bytes for newer Intel platforms, with older ones using 4 byte alignment.
+	 */
+	if (chip_info->hw_ip_version >= SOF_INTEL_ACE_4_0)
+		snd_pcm_hw_constraint_step(substream->runtime, 0,
+					   SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 128);
+	else
+		snd_pcm_hw_constraint_step(substream->runtime, 0,
+					   SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 4);
 
 	/* avoid circular buffer wrap in middle of period */
 	snd_pcm_hw_constraint_integer(substream->runtime,
-- 
2.53.0

Re: [PATCH for 7.0 1/2] ALSA: hda/intel: enforce stricter period-size alignment for Intel NVL

[Greg KH]

On Wed, Apr 08, 2026 at 11:45:13AM +0300, Peter Ujfalusi wrote:
> From: Kai Vehmanen <kai.vehmanen@linux.intel.com>
> 
> Intel ACE4 based products set more strict constraints on HDA BDLE start
> address and length alignment. Modify capability flags to drop
> AZX_DCAPS_NO_ALIGN_BUFSIZE for Intel Nova Lake platforms.
> 
> Fixes: 7f428282fde3 ("ALSA: hda: controllers: intel: add support for Nova Lake")
> Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
> Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
> Reviewed-by: Liam Girdwood <liam.r.girdwood@intel.com>

This also needs a:

Cc: stable <stable@kernel.org>

As the commit you reference here is in the stable 6.19.y tree.

thanks,

greg k-h

Re: [PATCH for 7.0 0/2] ALSA/SOF Intel: Enforce stricter period size for NVL

[Takashi Iwai]

On Wed, 08 Apr 2026 10:45:12 +0200,
Peter Ujfalusi wrote:
> 
> Hi,
> 
> NVL and NVL-S (ACE4) needs to use stricter period size constraint to
> meet the address alignment for each BDLE buffer (start of each period in
> the continuous ALSA buffer) set in the HDA specification.
> 
> It would be great if these can be sent for 7.0 as last minute if it is
> doable, I left out the Fixes tag from the first patch as that is
> introduced in 7.0.

Mark, shall I pick up both patches to my tree for the next PR (planned
for tomorrow or on Friday)?
Basically both patches are independent, and I can apply the first one
in anyway.


thanks,

Takashi

> 
> Regards
> Peter
> ---
> Kai Vehmanen (2):
>   ALSA: hda/intel: enforce stricter period-size alignment for Intel NVL
>   ASoC: SOF: Intel: hda: modify period size constraints for ACE4
> 
>  sound/hda/controllers/intel.c |  7 +++++--
>  sound/soc/sof/intel/hda-pcm.c | 14 ++++++++++++--
>  2 files changed, 17 insertions(+), 4 deletions(-)
> 
> -- 
> 2.53.0
> 

Re: [PATCH for 7.0 0/2] ALSA/SOF Intel: Enforce stricter period size for NVL

[Mark Brown]

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On Wed, Apr 08, 2026 at 01:41:22PM +0200, Takashi Iwai wrote:
> Peter Ujfalusi wrote:

> > NVL and NVL-S (ACE4) needs to use stricter period size constraint to
> > meet the address alignment for each BDLE buffer (start of each period in
> > the continuous ALSA buffer) set in the HDA specification.

> > It would be great if these can be sent for 7.0 as last minute if it is
> > doable, I left out the Fixes tag from the first patch as that is
> > introduced in 7.0.

> Mark, shall I pick up both patches to my tree for the next PR (planned
> for tomorrow or on Friday)?
> Basically both patches are independent, and I can apply the first one
> in anyway.

I've already got the ASoC one in process for a final fixes PR today and
was going to complain at Peter about combining patches for multiple
trees into a single series when there's no dependencies.

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Re: [PATCH for 7.0 0/2] ALSA/SOF Intel: Enforce stricter period size for NVL

[Takashi Iwai]

On Wed, 08 Apr 2026 14:05:59 +0200,
Mark Brown wrote:
> 
> On Wed, Apr 08, 2026 at 01:41:22PM +0200, Takashi Iwai wrote:
> > Peter Ujfalusi wrote:
> 
> > > NVL and NVL-S (ACE4) needs to use stricter period size constraint to
> > > meet the address alignment for each BDLE buffer (start of each period in
> > > the continuous ALSA buffer) set in the HDA specification.
> 
> > > It would be great if these can be sent for 7.0 as last minute if it is
> > > doable, I left out the Fixes tag from the first patch as that is
> > > introduced in 7.0.
> 
> > Mark, shall I pick up both patches to my tree for the next PR (planned
> > for tomorrow or on Friday)?
> > Basically both patches are independent, and I can apply the first one
> > in anyway.
> 
> I've already got the ASoC one in process for a final fixes PR today and
> was going to complain at Peter about combining patches for multiple
> trees into a single series when there's no dependencies.

OK, then I'll wait for your PR for the second patch, while I take the
first one on mine.


thanks,

Takashi

Re: [PATCH for 7.0 1/2] ALSA: hda/intel: enforce stricter period-size alignment for Intel NVL

[Takashi Iwai]

On Wed, 08 Apr 2026 10:45:13 +0200,
Peter Ujfalusi wrote:
> 
> From: Kai Vehmanen <kai.vehmanen@linux.intel.com>
> 
> Intel ACE4 based products set more strict constraints on HDA BDLE start
> address and length alignment. Modify capability flags to drop
> AZX_DCAPS_NO_ALIGN_BUFSIZE for Intel Nova Lake platforms.
> 
> Fixes: 7f428282fde3 ("ALSA: hda: controllers: intel: add support for Nova Lake")
> Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
> Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
> Reviewed-by: Liam Girdwood <liam.r.girdwood@intel.com>

Applied this one now (with Cc to stable).


thanks,

Takashi

Re: (subset) [PATCH for 7.0 0/2] ALSA/SOF Intel: Enforce stricter period size for NVL

[Mark Brown]

On Wed, 08 Apr 2026 11:45:12 +0300, Peter Ujfalusi wrote:
> ALSA/SOF Intel: Enforce stricter period size for NVL
> 
> Hi,
> 
> NVL and NVL-S (ACE4) needs to use stricter period size constraint to
> meet the address alignment for each BDLE buffer (start of each period in
> the continuous ALSA buffer) set in the HDA specification.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-7.0

Thanks!

[2/2] ASoC: SOF: Intel: hda: modify period size constraints for ACE4
      https://git.kernel.org/broonie/sound/c/0f7186605726

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark