From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 942652BE639 for ; Mon, 3 Aug 2026 23:38:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785800297; cv=none; b=gU2Acqjrc56g27OyhHz+BsCnXYQmFB12DVQG2ixpHrI/Fr4RiCGmiui4ApHcycI55X/y9R9J3FL4xKLeAoAxoKyhPUhuVqS6HJVC4z4gaOmubxc9gUDO8YSZtgpKlXQUUjTWLnUBqLnLcwI6UJkO0tuu2T6gCQmnQ9W3PHTZbjk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785800297; c=relaxed/simple; bh=Cy1oAtxcnMK5nPcTLXnW4zbsd9CKyOG8CpKg2UWPqq4=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=YFbAaqszZ6z9uwzU6hq8yBJakE9MT1v8aDiVRnUXKajxLZNj4CIIWZafTrdssMylrGQ2/o6litL16B6gj3hOPs8FiLRr6OMsMfDP559fAIW69DZpZLRq+EM62tm05lAa0/J9NjR3hXlD2qRPn7WCBftxu9HHe1r30sfiFkyflFI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=kI63eaxC; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="kI63eaxC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1785800296; x=1817336296; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version:content-transfer-encoding; bh=Cy1oAtxcnMK5nPcTLXnW4zbsd9CKyOG8CpKg2UWPqq4=; b=kI63eaxCCDcWLREoiBPp9zVBTPyDqao7BrQHjJbCW9k4O6ZWY+/YgX/3 vxzsh1Mh0Tbchd7vWZsY4I6kauQ9GRCAn6TC0cGEhJwFCiqkaWY0O0fu+ Ts9ulvm56+2iDhJEAHcxiPuaOKl59cQyAju3fB7TqNqY8R8fwiH4QNsvb YoaaI5pKqwD9rno+LPDYj+gIbBZQxfoybpBHAKpFw0puuzS0X9xDbK+H7 kvyWgCOPU1n8YbmZOOZ6ij06+53LaGU/6KP/dQVU1KvD/i+inhKbr4raZ 0WC7muHLnbxlnixtkJKpXatn8CiQJi3E9YZvxbK5kI09Wb6/TvomI3GFn w==; X-CSE-ConnectionGUID: C1jmTc3tQp2DO9/H9b7IYw== X-CSE-MsgGUID: zLWvI2+aSau2SdLlt88cAQ== X-IronPort-AV: E=McAfee;i="6800,10657,11864"; a="86113344" X-IronPort-AV: E=Sophos;i="6.25,203,1779174000"; d="scan'208";a="86113344" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2026 16:38:16 -0700 X-CSE-ConnectionGUID: 3ly6EoD3QuSvhYMwBw7opA== X-CSE-MsgGUID: /tdSAT9bTsGeXLMLT8weFQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,203,1779174000"; d="scan'208";a="264839385" Received: from unknown (HELO adixit-MOBL3.intel.com) ([10.241.243.62]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2026 16:38:15 -0700 Date: Mon, 03 Aug 2026 16:38:14 -0700 Message-ID: <87ldam22s9.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Sasha Levin Cc:, Umesh Nerlige Ramappa , Thomas =?ISO-8859-1?Q?Hellstr=F6m?= , Greg Kroah-Hartman Subject: Re: [PATCH 7.1.y] drm/xe/rtp: Maintain OA whitelists separately In-Reply-To: <87mrv2242a.wl-ashutosh.dixit@intel.com> References: <2026072958-unmasked-acting-7c2a@gregkh> <20260801004526.3662973-1-sashal@kernel.org> <87mrv2242a.wl-ashutosh.dixit@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable On Mon, 03 Aug 2026 16:10:37 -0700, Dixit, Ashutosh wrote: > > On Fri, 31 Jul 2026 17:45:26 -0700, Sasha Levin wrote: > > > > Hi Sasha/Greg, > > The patch below is correct. However, because you will encounter conflicts > in other patches of this series too, I have backported the entire series > for linux-7.1.y here: > > https://lore.kernel.org/stable/20260803230136.3270230-1-ashutosh.dixit@in= tel.com/ > > Will it be possible to apply the patches from the above link instead? > Since it will save us some work. > > I will also send backports of this series to linux-6.12.y and linux-6.18.= y. Ports to linux-6.12.y and linux-6.18.y are here: https://lore.kernel.org/stable/20260803233346.3277427-1-ashutosh.dixit@inte= l.com/ https://lore.kernel.org/stable/20260803232608.3276045-1-ashutosh.dixit@inte= l.com/ > Sorry, I am not too sure of the process to follow here. So if it needs to > be done differently please let me know. > > Thanks. > -- > Ashutosh > > > From: Ashutosh Dixit > > > > [ Upstream commit 31e2437561621b4867c08efc890bf629d017df03 ] > > > > OA registers are dynamically whitelisted (and again dewhitelisted) on OA > > stream open/close. Maintaining OA whitelists separately from non-OA > > register whitlists simplifies this management of OA register > > whitelisting/dewhitelisting. > > > > Fixes: 828a8eaf37c3 ("drm/xe/oa: Add MMIO trigger support") > > Cc: stable@vger.kernel.org # v6.12+ > > Signed-off-by: Ashutosh Dixit > > Reviewed-by: Umesh Nerlige Ramappa > > Link: https://patch.msgid.link/20260615224227.34880-3-ashutosh.dixit@in= tel.com > > (cherry picked from commit c478244a9e2d14b3f1f92e8bd293919e554622a5) > > Signed-off-by: Thomas Hellstr=F6m > > [ adapted RTP table from struct wrapper macro `XE_RTP_TABLE_SR()` back = to plain `struct xe_rtp_entry_sr[]` array and restored the 5-arg `xe_rtp_pr= ocess_to_sr()` call with `ARRAY_SIZE()` ] > > Signed-off-by: Sasha Levin > > --- > > drivers/gpu/drm/xe/xe_gt_debugfs.c | 4 +++- > > drivers/gpu/drm/xe/xe_hw_engine.c | 2 ++ > > drivers/gpu/drm/xe/xe_hw_engine_types.h | 8 ++++++++ > > drivers/gpu/drm/xe/xe_reg_whitelist.c | 6 ++++++ > > 4 files changed, 19 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/xe/xe_gt_debugfs.c b/drivers/gpu/drm/xe/xe= _gt_debugfs.c > > index f45306308cd6..c38bcacb27e4 100644 > > --- a/drivers/gpu/drm/xe/xe_gt_debugfs.c > > +++ b/drivers/gpu/drm/xe/xe_gt_debugfs.c > > @@ -149,8 +149,10 @@ static int register_save_restore(struct xe_gt *gt,= struct drm_printer *p) > > drm_printf(p, "\n"); > > > > drm_printf(p, "Whitelist\n"); > > - for_each_hw_engine(hwe, gt, id) > > + for_each_hw_engine(hwe, gt, id) { > > xe_reg_whitelist_dump(&hwe->reg_whitelist, p); > > + xe_reg_whitelist_dump(&hwe->oa_whitelist, p); > > + } > > > > return 0; > > } > > diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_= hw_engine.c > > index a7441a66e94c..b5a869c720af 100644 > > --- a/drivers/gpu/drm/xe/xe_hw_engine.c > > +++ b/drivers/gpu/drm/xe/xe_hw_engine.c > > @@ -575,6 +575,8 @@ static void hw_engine_init_early(struct xe_gt *gt, = struct xe_hw_engine *hwe, > > hw_engine_setup_default_state(hwe); > > > > xe_reg_sr_init(&hwe->reg_whitelist, hwe->name, gt_to_xe(gt)); > > + xe_reg_sr_init(&hwe->oa_whitelist, hwe->name, gt_to_xe(gt)); > > + xe_reg_sr_init(&hwe->oa_sr, hwe->name, gt_to_xe(gt)); > > xe_reg_whitelist_process_engine(hwe); > > } > > > > diff --git a/drivers/gpu/drm/xe/xe_hw_engine_types.h b/drivers/gpu/drm/= xe/xe_hw_engine_types.h > > index e4191a7a2c31..04ca7545d22c 100644 > > --- a/drivers/gpu/drm/xe/xe_hw_engine_types.h > > +++ b/drivers/gpu/drm/xe/xe_hw_engine_types.h > > @@ -128,6 +128,14 @@ struct xe_hw_engine { > > * @reg_whitelist: table with registers to be whitelisted > > */ > > struct xe_reg_sr reg_whitelist; > > + /** > > + * @oa_whitelist: oa registers to be whitelisted > > + */ > > + struct xe_reg_sr oa_whitelist; > > + /** > > + * @oa_sr: oa nonpriv whitelist registers, changed on oa stream open/= close > > + */ > > + struct xe_reg_sr oa_sr; > > /** > > * @reg_lrc: LRC workaround registers > > */ > > diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe= /xe_reg_whitelist.c > > index 8cc313182968..089335b185d1 100644 > > --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c > > +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c > > @@ -89,6 +89,9 @@ static const struct xe_rtp_entry_sr register_whitelis= t[] =3D { > > WHITELIST(VFLSKPD, > > RING_FORCE_TO_NONPRIV_ACCESS_RW)) > > }, > > +}; > > + > > +static const struct xe_rtp_entry_sr oa_whitelist[] =3D { > > > > #define WHITELIST_OA_MMIO_TRG(trg, status, head) \ > > WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW), \ > > @@ -191,6 +194,9 @@ void xe_reg_whitelist_process_engine(struct xe_hw_e= ngine *hwe) > > xe_rtp_process_to_sr(&ctx, register_whitelist, ARRAY_SIZE(register_whit= elist), > > &hwe->reg_whitelist, false); > > whitelist_apply_to_hwe(hwe); > > + > > + xe_rtp_process_to_sr(&ctx, oa_whitelist, ARRAY_SIZE(oa_whitelist), > > + &hwe->oa_whitelist, false); > > } > > > > /** > > -- > > 2.53.0 > >