From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com ([192.55.52.88]:48070 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752767AbdBTOnJ (ORCPT ); Mon, 20 Feb 2017 09:43:09 -0500 From: Mika Kuoppala To: Chris Wilson , intel-gfx@lists.freedesktop.org Cc: Chris Wilson , stable@vger.kernel.org Subject: Re: [PATCH 7/7] drm/i915: Stop RPS as we adjust thresholds In-Reply-To: <20170220094713.22874-7-chris@chris-wilson.co.uk> References: <20170220094713.22874-1-chris@chris-wilson.co.uk> <20170220094713.22874-7-chris@chris-wilson.co.uk> Date: Mon, 20 Feb 2017 16:41:47 +0200 Message-ID: <87r32sdivo.fsf@gaia.fi.intel.com> MIME-Version: 1.0 Content-Type: text/plain Sender: stable-owner@vger.kernel.org List-ID: Chris Wilson writes: > Disable RPS by setting RP_CONTROL to 0, remembering its earlier value. > Then adjust the thresholds before re-enabling RP_CONTROL. > > Signed-off-by: Chris Wilson > Cc: Mika Kuoppala > Cc: stable@vger.kernel.org Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index d37e95b3525d..e5cfa0377367 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4804,6 +4804,7 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) > int new_power; > u32 threshold_up = 0, threshold_down = 0; /* in % */ > u32 ei_up = 0, ei_down = 0; > + u32 rp_control; > > new_power = dev_priv->rps.power; > switch (dev_priv->rps.power) { > @@ -4872,6 +4873,12 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) > spin_lock_irq(&dev_priv->uncore.lock); > intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL); > > + /* Stop RPS before changing thresholds */ > + rp_control = I915_READ_FW(GEN6_RP_CONTROL); > + I915_WRITE_FW(GEN6_RP_CONTROL, 0); > + POSTING_READ_FW(GEN6_RP_CONTROL); > + > + /* Update thresholds and evaluation intervals */ > I915_WRITE_FW(GEN6_RP_UP_EI, > GT_INTERVAL_FROM_US(dev_priv, ei_up)); > I915_WRITE_FW(GEN6_RP_UP_THRESHOLD, > @@ -4885,8 +4892,7 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) > ei_down * threshold_down / 100)); > > /* Restart RPS to reload the thresholds */ > - I915_WRITE_FW(GEN6_RP_CONTROL, > - I915_READ_FW(GEN6_RP_CONTROL) | GEN6_RP_ENABLE); > + I915_WRITE_FW(GEN6_RP_CONTROL, rp_control | GEN6_RP_ENABLE); > > intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL); > spin_unlock_irq(&dev_priv->uncore.lock); > -- > 2.11.0