From: Felipe Balbi <felipe.balbi@linux.intel.com>
To: Bjorn Helgaas <bhelgaas@google.com>
Cc: Bjorn Helgaas <helgaas@kernel.org>,
linux-pci@vger.kernel.org, stable@vger.kernel.org,
Jingoo Han <jingoohan1@gmail.com>
Subject: Re: [PATCH] PCI: Fix bit definitions for LNKCAP2 register
Date: Wed, 08 Aug 2018 09:30:56 +0300 [thread overview]
Message-ID: <87va8l8j4v.fsf@linux.intel.com> (raw)
In-Reply-To: <CAErSpo595gmyeWNtY4Ur6VQoxS82bx8JQ-PoSv0oUdn-j7pJCA@mail.gmail.com>
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Hi,
Bjorn Helgaas <bhelgaas@google.com> writes:
>> Bjorn Helgaas <helgaas@kernel.org> writes:
>> > On Fri, Aug 03, 2018 at 09:51:20AM +0300, Felipe Balbi wrote:
>> >> Even thhough commit b891b4dc1eed claimed that original bit definitions
>> >> were wrong, that's not really the case. After verifying PCI
>> >> Specification Revisions 3.0, 3.1 and 4.0, Link Capabilites 2
>> >> Register's bit definitions were always starting from Bit 0.
>> >>
>> >> This has been causing issues reporting correct link speeds on sysfs.
>> >
>> > Can you elaborate on this a bit? b891b4dc1eed still looks correct to
>> > me. I'm looking at PCIe r4.0, sec 7.5.3.18, where it shows:
>> >
>> > bit 0 RsvdP
>> > bits 7:1 Supported Link Speeds Vector
>>
>> I had missed this detail, actually. It was a misinterpretation of the
>> spec. Sorry for the noise.
>
> No problem. You were seeing something incorrect in sysfs, so if we
> can help diagnose or fix whatever the real problem is, don't hesitate
> to ask!
Sure thing, but I think this is a problem elsewhere :)
--
balbi
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prev parent reply other threads:[~2018-08-08 8:52 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-03 6:51 [PATCH] PCI: Fix bit definitions for LNKCAP2 register Felipe Balbi
2018-08-06 18:23 ` Bjorn Helgaas
2018-08-07 8:20 ` Felipe Balbi
2018-08-07 18:18 ` Jingoo Han
2018-08-07 20:13 ` Bjorn Helgaas
2018-08-08 6:30 ` Felipe Balbi [this message]
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