* [PATCH 09/11] drm/i915/skl: Prevent unclaimed register writes on skylake.
[not found] <1445514996-18733-1-git-send-email-maarten.lankhorst@linux.intel.com>
@ 2015-10-22 11:56 ` Maarten Lankhorst
2015-10-22 13:11 ` [Intel-gfx] " Daniel Vetter
2015-10-22 11:56 ` [PATCH 10/11] drm/i915/skl: Update watermarks before the crtc is disabled Maarten Lankhorst
1 sibling, 1 reply; 6+ messages in thread
From: Maarten Lankhorst @ 2015-10-22 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: Maarten Lankhorst, stable
I'm getting unclaimed register writes when checking the WM registers
after the crtc is disabled. So I would imagine those are guarded by
the crtc power well. Fix this by not reading out wm state when the
power well is off.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92181
Cc: stable@vger.kernel.org
---
drivers/gpu/drm/i915/intel_pm.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4c1c1bb96a9e..fbc10331055e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2833,7 +2833,12 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
int plane;
u32 val;
+ memset(ddb, 0, sizeof(*ddb));
+
for_each_pipe(dev_priv, pipe) {
+ if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe)))
+ continue;
+
for_each_plane(dev_priv, pipe, plane) {
val = I915_READ(PLANE_BUF_CFG(pipe, plane));
skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
--
2.1.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 10/11] drm/i915/skl: Update watermarks before the crtc is disabled.
[not found] <1445514996-18733-1-git-send-email-maarten.lankhorst@linux.intel.com>
2015-10-22 11:56 ` [PATCH 09/11] drm/i915/skl: Prevent unclaimed register writes on skylake Maarten Lankhorst
@ 2015-10-22 11:56 ` Maarten Lankhorst
2015-10-22 13:15 ` [Intel-gfx] " Daniel Vetter
1 sibling, 1 reply; 6+ messages in thread
From: Maarten Lankhorst @ 2015-10-22 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: Maarten Lankhorst, stable, Matt Roper
On skylake some of the registers are only writable when the correct
power wells are enabled. Because of this watermarks have to be updated
before the crtc turns off, or you get unclaimed register read and write
warnings.
This patch needs to be modified slightly to apply to -fixes.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92181
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: stable@vger.kernel.org
Cc: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6f92ccf2461c..26931d8eb7ce 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4761,7 +4761,7 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
crtc->wm.cxsr_allowed = true;
- if (pipe_config->wm_changed)
+ if (pipe_config->wm_changed && pipe_config->base.active)
intel_update_watermarks(&crtc->base);
for_each_plane_in_state(old_state, plane, old_plane_state, i) {
@@ -13205,6 +13205,9 @@ static int intel_atomic_commit(struct drm_device *dev,
dev_priv->display.crtc_disable(crtc);
intel_crtc->active = false;
intel_disable_shared_dpll(intel_crtc);
+
+ if (!crtc->state->active)
+ intel_update_watermarks(crtc);
}
}
--
2.1.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH 09/11] drm/i915/skl: Prevent unclaimed register writes on skylake.
2015-10-22 11:56 ` [PATCH 09/11] drm/i915/skl: Prevent unclaimed register writes on skylake Maarten Lankhorst
@ 2015-10-22 13:11 ` Daniel Vetter
2015-10-23 7:54 ` Jani Nikula
0 siblings, 1 reply; 6+ messages in thread
From: Daniel Vetter @ 2015-10-22 13:11 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx, stable, Jani Nikula
On Thu, Oct 22, 2015 at 01:56:34PM +0200, Maarten Lankhorst wrote:
> I'm getting unclaimed register writes when checking the WM registers
> after the crtc is disabled. So I would imagine those are guarded by
> the crtc power well. Fix this by not reading out wm state when the
> power well is off.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92181
> Cc: stable@vger.kernel.org
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jani, one for you.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_pm.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 4c1c1bb96a9e..fbc10331055e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2833,7 +2833,12 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
> int plane;
> u32 val;
>
> + memset(ddb, 0, sizeof(*ddb));
> +
> for_each_pipe(dev_priv, pipe) {
> + if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe)))
> + continue;
> +
> for_each_plane(dev_priv, pipe, plane) {
> val = I915_READ(PLANE_BUF_CFG(pipe, plane));
> skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
> --
> 2.1.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH 10/11] drm/i915/skl: Update watermarks before the crtc is disabled.
2015-10-22 11:56 ` [PATCH 10/11] drm/i915/skl: Update watermarks before the crtc is disabled Maarten Lankhorst
@ 2015-10-22 13:15 ` Daniel Vetter
0 siblings, 0 replies; 6+ messages in thread
From: Daniel Vetter @ 2015-10-22 13:15 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx, stable
On Thu, Oct 22, 2015 at 01:56:35PM +0200, Maarten Lankhorst wrote:
> On skylake some of the registers are only writable when the correct
> power wells are enabled. Because of this watermarks have to be updated
> before the crtc turns off, or you get unclaimed register read and write
> warnings.
>
> This patch needs to be modified slightly to apply to -fixes.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92181
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: stable@vger.kernel.org
> Cc: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 6f92ccf2461c..26931d8eb7ce 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4761,7 +4761,7 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
>
> crtc->wm.cxsr_allowed = true;
>
> - if (pipe_config->wm_changed)
> + if (pipe_config->wm_changed && pipe_config->base.active)
> intel_update_watermarks(&crtc->base);
Calling post_plane_commit seems like a bug of the higher-level functions.
If we can't fix that quickly I think we should have at least an early exit
at the top, with a FIXME comment.
If the platform/feature-specific commit hooks have to care about
state->active, then the higher level functions imo haven't done their jobs
properly.
>
> for_each_plane_in_state(old_state, plane, old_plane_state, i) {
> @@ -13205,6 +13205,9 @@ static int intel_atomic_commit(struct drm_device *dev,
> dev_priv->display.crtc_disable(crtc);
> intel_crtc->active = false;
> intel_disable_shared_dpll(intel_crtc);
> +
> + if (!crtc->state->active)
> + intel_update_watermarks(crtc);
Does this ever do anything at all? We just killed the crtc completely
above, those watermark writes will get cleansed as soon as the power well
goes down.
-Daniel
> }
> }
>
> --
> 2.1.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH 09/11] drm/i915/skl: Prevent unclaimed register writes on skylake.
2015-10-22 13:11 ` [Intel-gfx] " Daniel Vetter
@ 2015-10-23 7:54 ` Jani Nikula
2015-11-02 8:01 ` Jani Nikula
0 siblings, 1 reply; 6+ messages in thread
From: Jani Nikula @ 2015-10-23 7:54 UTC (permalink / raw)
To: Daniel Vetter, Maarten Lankhorst; +Cc: intel-gfx, stable
On Thu, 22 Oct 2015, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Thu, Oct 22, 2015 at 01:56:34PM +0200, Maarten Lankhorst wrote:
>> I'm getting unclaimed register writes when checking the WM registers
>> after the crtc is disabled. So I would imagine those are guarded by
>> the crtc power well. Fix this by not reading out wm state when the
>> power well is off.
>>
>> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92181
>> Cc: stable@vger.kernel.org
>
> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>
> Jani, one for you.
This one pushed to drm-intel-fixes, thanks for the patch and review.
I dropped cc: stable because this will still make it to v4.3, and we're
not backporting SKL fixes beyond that.
BR,
Jani.
> -Daniel
>
>> ---
>> drivers/gpu/drm/i915/intel_pm.c | 5 +++++
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 4c1c1bb96a9e..fbc10331055e 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -2833,7 +2833,12 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
>> int plane;
>> u32 val;
>>
>> + memset(ddb, 0, sizeof(*ddb));
>> +
>> for_each_pipe(dev_priv, pipe) {
>> + if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe)))
>> + continue;
>> +
>> for_each_plane(dev_priv, pipe, plane) {
>> val = I915_READ(PLANE_BUF_CFG(pipe, plane));
>> skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
>> --
>> 2.1.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH 09/11] drm/i915/skl: Prevent unclaimed register writes on skylake.
2015-10-23 7:54 ` Jani Nikula
@ 2015-11-02 8:01 ` Jani Nikula
0 siblings, 0 replies; 6+ messages in thread
From: Jani Nikula @ 2015-11-02 8:01 UTC (permalink / raw)
To: Daniel Vetter, Maarten Lankhorst; +Cc: intel-gfx, stable
On Fri, 23 Oct 2015, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Thu, 22 Oct 2015, Daniel Vetter <daniel@ffwll.ch> wrote:
>> On Thu, Oct 22, 2015 at 01:56:34PM +0200, Maarten Lankhorst wrote:
>>> I'm getting unclaimed register writes when checking the WM registers
>>> after the crtc is disabled. So I would imagine those are guarded by
>>> the crtc power well. Fix this by not reading out wm state when the
>>> power well is off.
>>>
>>> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92181
>>> Cc: stable@vger.kernel.org
>>
>> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>>
>> Jani, one for you.
>
> This one pushed to drm-intel-fixes, thanks for the patch and review.
>
> I dropped cc: stable because this will still make it to v4.3, and we're
> not backporting SKL fixes beyond that.
This didn't make it to v4.3 after all. Dropped from drm-intel-fixes,
pushed to drm-intel-next-fixes, and marked cc: stable for v4.3.
BR,
Jani.
>
> BR,
> Jani.
>
>
>> -Daniel
>>
>>> ---
>>> drivers/gpu/drm/i915/intel_pm.c | 5 +++++
>>> 1 file changed, 5 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>>> index 4c1c1bb96a9e..fbc10331055e 100644
>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>> @@ -2833,7 +2833,12 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
>>> int plane;
>>> u32 val;
>>>
>>> + memset(ddb, 0, sizeof(*ddb));
>>> +
>>> for_each_pipe(dev_priv, pipe) {
>>> + if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe)))
>>> + continue;
>>> +
>>> for_each_plane(dev_priv, pipe, plane) {
>>> val = I915_READ(PLANE_BUF_CFG(pipe, plane));
>>> skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
>>> --
>>> 2.1.0
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 6+ messages in thread
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[not found] <1445514996-18733-1-git-send-email-maarten.lankhorst@linux.intel.com>
2015-10-22 11:56 ` [PATCH 09/11] drm/i915/skl: Prevent unclaimed register writes on skylake Maarten Lankhorst
2015-10-22 13:11 ` [Intel-gfx] " Daniel Vetter
2015-10-23 7:54 ` Jani Nikula
2015-11-02 8:01 ` Jani Nikula
2015-10-22 11:56 ` [PATCH 10/11] drm/i915/skl: Update watermarks before the crtc is disabled Maarten Lankhorst
2015-10-22 13:15 ` [Intel-gfx] " Daniel Vetter
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