From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com ([134.134.136.20]:11064 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752370AbbJWHvl (ORCPT ); Fri, 23 Oct 2015 03:51:41 -0400 From: Jani Nikula To: Daniel Vetter , Maarten Lankhorst Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org Subject: Re: [Intel-gfx] [PATCH 09/11] drm/i915/skl: Prevent unclaimed register writes on skylake. In-Reply-To: <20151022131118.GV16848@phenom.ffwll.local> References: <1445514996-18733-1-git-send-email-maarten.lankhorst@linux.intel.com> <1445514996-18733-10-git-send-email-maarten.lankhorst@linux.intel.com> <20151022131118.GV16848@phenom.ffwll.local> Date: Fri, 23 Oct 2015 10:54:57 +0300 Message-ID: <87vb9yuii6.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain Sender: stable-owner@vger.kernel.org List-ID: On Thu, 22 Oct 2015, Daniel Vetter wrote: > On Thu, Oct 22, 2015 at 01:56:34PM +0200, Maarten Lankhorst wrote: >> I'm getting unclaimed register writes when checking the WM registers >> after the crtc is disabled. So I would imagine those are guarded by >> the crtc power well. Fix this by not reading out wm state when the >> power well is off. >> >> Signed-off-by: Maarten Lankhorst >> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92181 >> Cc: stable@vger.kernel.org > > Reviewed-by: Daniel Vetter > > Jani, one for you. This one pushed to drm-intel-fixes, thanks for the patch and review. I dropped cc: stable because this will still make it to v4.3, and we're not backporting SKL fixes beyond that. BR, Jani. > -Daniel > >> --- >> drivers/gpu/drm/i915/intel_pm.c | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c >> index 4c1c1bb96a9e..fbc10331055e 100644 >> --- a/drivers/gpu/drm/i915/intel_pm.c >> +++ b/drivers/gpu/drm/i915/intel_pm.c >> @@ -2833,7 +2833,12 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, >> int plane; >> u32 val; >> >> + memset(ddb, 0, sizeof(*ddb)); >> + >> for_each_pipe(dev_priv, pipe) { >> + if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) >> + continue; >> + >> for_each_plane(dev_priv, pipe, plane) { >> val = I915_READ(PLANE_BUF_CFG(pipe, plane)); >> skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane], >> -- >> 2.1.0 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center