From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com ([134.134.136.24]:2857 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751239AbcGMIIi (ORCPT ); Wed, 13 Jul 2016 04:08:38 -0400 From: Mika Kuoppala To: Daniel Vetter , Chris Wilson Cc: Daniel Vetter , dri-devel@lists.freedesktop.org, Jason Ekstrand , Akash Goel , stable@vger.kernel.org, intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH 06/64] drm: Restore double clflush on the last partial cacheline In-Reply-To: <20160712135744.GI23520@phenom.ffwll.local> References: <1467880930-23082-1-git-send-email-chris@chris-wilson.co.uk> <1467880930-23082-6-git-send-email-chris@chris-wilson.co.uk> <20160712135744.GI23520@phenom.ffwll.local> Date: Wed, 13 Jul 2016 11:07:44 +0300 Message-ID: <87wpkqrmen.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain Sender: stable-owner@vger.kernel.org List-ID: Daniel Vetter writes: > On Thu, Jul 07, 2016 at 09:41:12AM +0100, Chris Wilson wrote: >> This effectively reverts >> >> commit afcd950cafea6e27b739fe7772cbbeed37d05b8b >> Author: Chris Wilson >> Date: Wed Jun 10 15:58:01 2015 +0100 >> >> drm: Avoid the double clflush on the last cache line in drm_clflush_virt_range() >> >> as we have observed issues with serialisation of the clflush operations >> on Baytrail+ Atoms with partial updates. Applying the double flush on the >> last cacheline forces that clflush to be ordered with respect to the >> previous clflush, and the mfence then protects against prefetches crossing >> the clflush boundary. >> >> The same issue can be demonstrated in userspace with igt/gem_exec_flush. >> >> Fixes: afcd950cafea6 (drm: Avoid the double clflush on the last cache...) >> Testcase: igt/gem_concurrent_blit >> Testcase: igt/gem_partial_pread_pwrite >> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92845 >> Signed-off-by: Chris Wilson >> Cc: dri-devel@lists.freedesktop.org >> Cc: Akash Goel >> Cc: Imre Deak >> Cc: Daniel Vetter >> Cc: Jason Ekstrand >> Cc: stable@vger.kernel.org >> Reviewed-by: Mika Kuoppala > > It's duct-tape, but oh well. Applied to drm-misc. We were confused how many layers we need. -Mika > -Daniel > >> --- >> drivers/gpu/drm/drm_cache.c | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c >> index 059f7c39c582..a7916e5f8864 100644 >> --- a/drivers/gpu/drm/drm_cache.c >> +++ b/drivers/gpu/drm/drm_cache.c >> @@ -136,6 +136,7 @@ drm_clflush_virt_range(void *addr, unsigned long length) >> mb(); >> for (; addr < end; addr += size) >> clflushopt(addr); >> + clflushopt(end - 1); /* force serialisation */ >> mb(); >> return; >> } >> -- >> 2.8.1 >> > > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx