* [PATCH] drm/i915: Limit the number of loops for reading a split 64bit register
@ 2015-09-08 7:24 Chris Wilson
2015-09-08 7:51 ` Chris Wilson
2015-09-08 12:36 ` [Intel-gfx] " Jani Nikula
0 siblings, 2 replies; 8+ messages in thread
From: Chris Wilson @ 2015-09-08 7:24 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson, Michał Winiarski, Daniel Vetter, stable
In I915_READ64_2x32 we attempt to read a 64bit register using 2 32bit
reads. Due to the nature of the registers we try to read in this manner,
they may increment between the two instruction (e.g. a timestamp
counter). To keep the result accurate, we repeat the read if we detect
an overflow (i.e. the upper value varies). However, some harware is just
plain flaky and may endless loop as the the upper 32bits are not stable.
Just give up after a couple of tries and report whatever we read last.
Reported-by: russianneuromancer@ya.ru
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91906
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: stable@vger.kernel.org
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 12870073d58f..8943dcb724a8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3402,13 +3402,13 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
- u32 upper, lower, tmp; \
+ u32 upper, lower, tmp, loop = 0; \
tmp = I915_READ(upper_reg); \
do { \
upper = tmp; \
lower = I915_READ(lower_reg); \
tmp = I915_READ(upper_reg); \
- } while (upper != tmp); \
+ } while (upper != tmp && loop++ != 2); \
(u64)upper << 32 | lower; })
#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
--
2.5.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: Limit the number of loops for reading a split 64bit register
2015-09-08 7:24 [PATCH] drm/i915: Limit the number of loops for reading a split 64bit register Chris Wilson
@ 2015-09-08 7:51 ` Chris Wilson
2015-09-08 9:29 ` Daniel Vetter
2015-09-08 12:36 ` [Intel-gfx] " Jani Nikula
1 sibling, 1 reply; 8+ messages in thread
From: Chris Wilson @ 2015-09-08 7:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Michał Winiarski, Daniel Vetter, stable
On Tue, Sep 08, 2015 at 08:24:19AM +0100, Chris Wilson wrote:
> In I915_READ64_2x32 we attempt to read a 64bit register using 2 32bit
> reads. Due to the nature of the registers we try to read in this manner,
> they may increment between the two instruction (e.g. a timestamp
> counter). To keep the result accurate, we repeat the read if we detect
> an overflow (i.e. the upper value varies). However, some harware is just
> plain flaky and may endless loop as the the upper 32bits are not stable.
> Just give up after a couple of tries and report whatever we read last.
>
> Reported-by: russianneuromancer@ya.ru
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91906
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: stable@vger.kernel.org
> ---
> drivers/gpu/drm/i915/i915_drv.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 12870073d58f..8943dcb724a8 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3402,13 +3402,13 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
>
> #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
> - u32 upper, lower, tmp; \
> + u32 upper, lower, tmp, loop = 0; \
> tmp = I915_READ(upper_reg); \
> do { \
> upper = tmp; \
> lower = I915_READ(lower_reg); \
> tmp = I915_READ(upper_reg); \
> - } while (upper != tmp); \
> + } while (upper != tmp && loop++ != 2); \
Maybe "loop++ < 2" for one more character of clarity.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: Limit the number of loops for reading a split 64bit register
2015-09-08 7:51 ` Chris Wilson
@ 2015-09-08 9:29 ` Daniel Vetter
0 siblings, 0 replies; 8+ messages in thread
From: Daniel Vetter @ 2015-09-08 9:29 UTC (permalink / raw)
To: Chris Wilson, intel-gfx, Michał Winiarski, Daniel Vetter,
stable
Cc: Jani Nikula
On Tue, Sep 08, 2015 at 08:51:50AM +0100, Chris Wilson wrote:
> On Tue, Sep 08, 2015 at 08:24:19AM +0100, Chris Wilson wrote:
> > In I915_READ64_2x32 we attempt to read a 64bit register using 2 32bit
> > reads. Due to the nature of the registers we try to read in this manner,
> > they may increment between the two instruction (e.g. a timestamp
> > counter). To keep the result accurate, we repeat the read if we detect
> > an overflow (i.e. the upper value varies). However, some harware is just
> > plain flaky and may endless loop as the the upper 32bits are not stable.
> > Just give up after a couple of tries and report whatever we read last.
> >
> > Reported-by: russianneuromancer@ya.ru
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91906
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Michał Winiarski <michal.winiarski@intel.com>
> > Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> > Cc: stable@vger.kernel.org
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 12870073d58f..8943dcb724a8 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -3402,13 +3402,13 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> > #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
> >
> > #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
> > - u32 upper, lower, tmp; \
> > + u32 upper, lower, tmp, loop = 0; \
> > tmp = I915_READ(upper_reg); \
> > do { \
> > upper = tmp; \
> > lower = I915_READ(lower_reg); \
> > tmp = I915_READ(upper_reg); \
> > - } while (upper != tmp); \
> > + } while (upper != tmp && loop++ != 2); \
>
> Maybe "loop++ < 2" for one more character of clarity.
Yeah s/!=/</ is a bit clearer. With that Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Limit the number of loops for reading a split 64bit register
2015-09-08 7:24 [PATCH] drm/i915: Limit the number of loops for reading a split 64bit register Chris Wilson
2015-09-08 7:51 ` Chris Wilson
@ 2015-09-08 12:36 ` Jani Nikula
2015-09-08 13:10 ` Chris Wilson
2015-09-08 13:17 ` [PATCH v2] " Chris Wilson
1 sibling, 2 replies; 8+ messages in thread
From: Jani Nikula @ 2015-09-08 12:36 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Daniel Vetter, stable
On Tue, 08 Sep 2015, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> In I915_READ64_2x32 we attempt to read a 64bit register using 2 32bit
> reads. Due to the nature of the registers we try to read in this manner,
> they may increment between the two instruction (e.g. a timestamp
> counter). To keep the result accurate, we repeat the read if we detect
> an overflow (i.e. the upper value varies). However, some harware is just
> plain flaky and may endless loop as the the upper 32bits are not stable.
> Just give up after a couple of tries and report whatever we read last.
>
> Reported-by: russianneuromancer@ya.ru
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91906
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: stable@vger.kernel.org
> ---
> drivers/gpu/drm/i915/i915_drv.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 12870073d58f..8943dcb724a8 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3402,13 +3402,13 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
>
> #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
> - u32 upper, lower, tmp; \
> + u32 upper, lower, tmp, loop = 0; \
> tmp = I915_READ(upper_reg); \
> do { \
> upper = tmp; \
> lower = I915_READ(lower_reg); \
> tmp = I915_READ(upper_reg); \
> - } while (upper != tmp); \
> + } while (upper != tmp && loop++ != 2); \
Do you think it matters that you'll take the previous, not the last,
value when you give up?
BR,
Jani.
> (u64)upper << 32 | lower; })
>
> #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
> --
> 2.5.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Limit the number of loops for reading a split 64bit register
2015-09-08 12:36 ` [Intel-gfx] " Jani Nikula
@ 2015-09-08 13:10 ` Chris Wilson
2015-09-08 13:17 ` [PATCH v2] " Chris Wilson
1 sibling, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2015-09-08 13:10 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, Daniel Vetter, stable
On Tue, Sep 08, 2015 at 03:36:32PM +0300, Jani Nikula wrote:
> On Tue, 08 Sep 2015, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > In I915_READ64_2x32 we attempt to read a 64bit register using 2 32bit
> > reads. Due to the nature of the registers we try to read in this manner,
> > they may increment between the two instruction (e.g. a timestamp
> > counter). To keep the result accurate, we repeat the read if we detect
> > an overflow (i.e. the upper value varies). However, some harware is just
> > plain flaky and may endless loop as the the upper 32bits are not stable.
> > Just give up after a couple of tries and report whatever we read last.
> >
> > Reported-by: russianneuromancer@ya.ru
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91906
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Michał Winiarski <michal.winiarski@intel.com>
> > Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> > Cc: stable@vger.kernel.org
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 12870073d58f..8943dcb724a8 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -3402,13 +3402,13 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> > #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
> >
> > #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
> > - u32 upper, lower, tmp; \
> > + u32 upper, lower, tmp, loop = 0; \
> > tmp = I915_READ(upper_reg); \
> > do { \
> > upper = tmp; \
> > lower = I915_READ(lower_reg); \
> > tmp = I915_READ(upper_reg); \
> > - } while (upper != tmp); \
> > + } while (upper != tmp && loop++ != 2); \
>
> Do you think it matters that you'll take the previous, not the last,
> value when you give up?
Not an awful lot, but it's a good reason to respin.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2] drm/i915: Limit the number of loops for reading a split 64bit register
2015-09-08 12:36 ` [Intel-gfx] " Jani Nikula
2015-09-08 13:10 ` Chris Wilson
@ 2015-09-08 13:17 ` Chris Wilson
2015-09-08 19:00 ` Daniel Vetter
1 sibling, 1 reply; 8+ messages in thread
From: Chris Wilson @ 2015-09-08 13:17 UTC (permalink / raw)
To: intel-gfx
Cc: Chris Wilson, Michał Winiarski, Daniel Vetter, Jani Nikula,
stable
In I915_READ64_2x32 we attempt to read a 64bit register using 2 32bit
reads. Due to the nature of the registers we try to read in this manner,
they may increment between the two instruction (e.g. a timestamp
counter). To keep the result accurate, we repeat the read if we detect
an overflow (i.e. the upper value varies). However, some harware is just
plain flaky and may endless loop as the the upper 32bits are not stable.
Just give up after a couple of tries and report whatever we read last.
v2: Use the most recent values when erring out on an unstable register.
Reported-by: russianneuromancer@ya.ru
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91906
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: stable@vger.kernel.org
---
drivers/gpu/drm/i915/i915_drv.h | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 12870073d58f..51a88e70a6f7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3402,13 +3402,13 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
- u32 upper, lower, tmp; \
- tmp = I915_READ(upper_reg); \
+ u32 upper, lower, old_upper, loop = 0; \
+ upper = I915_READ(upper_reg); \
do { \
- upper = tmp; \
+ old_upper = upper; \
lower = I915_READ(lower_reg); \
- tmp = I915_READ(upper_reg); \
- } while (upper != tmp); \
+ upper = I915_READ(upper_reg); \
+ } while (upper != old_upper && loop++ < 2); \
(u64)upper << 32 | lower; })
#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
--
2.5.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2] drm/i915: Limit the number of loops for reading a split 64bit register
2015-09-08 13:17 ` [PATCH v2] " Chris Wilson
@ 2015-09-08 19:00 ` Daniel Vetter
2015-09-09 8:13 ` Jani Nikula
0 siblings, 1 reply; 8+ messages in thread
From: Daniel Vetter @ 2015-09-08 19:00 UTC (permalink / raw)
To: Chris Wilson
Cc: intel-gfx, Michał Winiarski, Daniel Vetter, Jani Nikula,
stable
On Tue, Sep 08, 2015 at 02:17:13PM +0100, Chris Wilson wrote:
> In I915_READ64_2x32 we attempt to read a 64bit register using 2 32bit
> reads. Due to the nature of the registers we try to read in this manner,
> they may increment between the two instruction (e.g. a timestamp
> counter). To keep the result accurate, we repeat the read if we detect
> an overflow (i.e. the upper value varies). However, some harware is just
> plain flaky and may endless loop as the the upper 32bits are not stable.
> Just give up after a couple of tries and report whatever we read last.
>
> v2: Use the most recent values when erring out on an unstable register.
>
> Reported-by: russianneuromancer@ya.ru
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91906
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: stable@vger.kernel.org
Still Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 12870073d58f..51a88e70a6f7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3402,13 +3402,13 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
>
> #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
> - u32 upper, lower, tmp; \
> - tmp = I915_READ(upper_reg); \
> + u32 upper, lower, old_upper, loop = 0; \
> + upper = I915_READ(upper_reg); \
> do { \
> - upper = tmp; \
> + old_upper = upper; \
> lower = I915_READ(lower_reg); \
> - tmp = I915_READ(upper_reg); \
> - } while (upper != tmp); \
> + upper = I915_READ(upper_reg); \
> + } while (upper != old_upper && loop++ < 2); \
> (u64)upper << 32 | lower; })
>
> #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
> --
> 2.5.1
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2] drm/i915: Limit the number of loops for reading a split 64bit register
2015-09-08 19:00 ` Daniel Vetter
@ 2015-09-09 8:13 ` Jani Nikula
0 siblings, 0 replies; 8+ messages in thread
From: Jani Nikula @ 2015-09-09 8:13 UTC (permalink / raw)
To: Daniel Vetter, Chris Wilson
Cc: intel-gfx, Michał Winiarski, Daniel Vetter, stable
On Tue, 08 Sep 2015, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Tue, Sep 08, 2015 at 02:17:13PM +0100, Chris Wilson wrote:
>> In I915_READ64_2x32 we attempt to read a 64bit register using 2 32bit
>> reads. Due to the nature of the registers we try to read in this manner,
>> they may increment between the two instruction (e.g. a timestamp
>> counter). To keep the result accurate, we repeat the read if we detect
>> an overflow (i.e. the upper value varies). However, some harware is just
>> plain flaky and may endless loop as the the upper 32bits are not stable.
>> Just give up after a couple of tries and report whatever we read last.
>>
>> v2: Use the most recent values when erring out on an unstable register.
>>
>> Reported-by: russianneuromancer@ya.ru
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91906
>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Michał Winiarski <michal.winiarski@intel.com>
>> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
>> Cc: stable@vger.kernel.org
>
> Still Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Pushed to drm-intel-next-fixes, thanks for the patch and review.
BR,
Jani.
>
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 10 +++++-----
>> 1 file changed, 5 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 12870073d58f..51a88e70a6f7 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -3402,13 +3402,13 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
>> #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
>>
>> #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
>> - u32 upper, lower, tmp; \
>> - tmp = I915_READ(upper_reg); \
>> + u32 upper, lower, old_upper, loop = 0; \
>> + upper = I915_READ(upper_reg); \
>> do { \
>> - upper = tmp; \
>> + old_upper = upper; \
>> lower = I915_READ(lower_reg); \
>> - tmp = I915_READ(upper_reg); \
>> - } while (upper != tmp); \
>> + upper = I915_READ(upper_reg); \
>> + } while (upper != old_upper && loop++ < 2); \
>> (u64)upper << 32 | lower; })
>>
>> #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
>> --
>> 2.5.1
>>
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2015-09-09 8:10 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
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2015-09-08 7:24 [PATCH] drm/i915: Limit the number of loops for reading a split 64bit register Chris Wilson
2015-09-08 7:51 ` Chris Wilson
2015-09-08 9:29 ` Daniel Vetter
2015-09-08 12:36 ` [Intel-gfx] " Jani Nikula
2015-09-08 13:10 ` Chris Wilson
2015-09-08 13:17 ` [PATCH v2] " Chris Wilson
2015-09-08 19:00 ` Daniel Vetter
2015-09-09 8:13 ` Jani Nikula
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