* [PATCH v3 2/2] drm/i915/dp: BDW cdclk fix for DP audio [not found] <87d1iooknr.fsf@intel.com> @ 2016-10-25 23:41 ` Dhinakaran Pandiyan 2016-10-26 8:54 ` Jani Nikula 0 siblings, 1 reply; 5+ messages in thread From: Dhinakaran Pandiyan @ 2016-10-25 23:41 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula, ville.syrjala, Dhinakaran Pandiyan, stable According to BSpec, cdclk has to be not less than 432 MHz with DP audio enabled, port width x4, and link rate HBR2 (5.4 GHz) Having a lower cdclk triggers pipe underruns, which then lead to displays continuously cycling off and on. This is essential for DP MST audio as the link is trained at HBR2 and 4 lanes by default. v3: Combine BDW pixel rate adjustments into a function (Jani) v2: Restrict fix to BDW Retain the set cdclk across modesets (Ville) Cc: stable@vger.kernel.org Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a94f7d1..efe46b4 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -10260,6 +10260,27 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) bxt_set_cdclk(to_i915(dev), req_cdclk); } +static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, + int pixel_rate) +{ + /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ + if (crtc_state->ips_enabled) + pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); + + /* BSpec says "Do not use DisplayPort with CDCLK less than + * 432 MHz, audio enabled, port width x4, and link rate + * HBR2 (5.4 GHz), or else there may be audio corruption or + * screen corruption." + */ + if (intel_crtc_has_dp_encoder(crtc_state) && + crtc_state->has_audio && + crtc_state->port_clock >= 540000 && + crtc_state->lane_count == 4) + pixel_rate = max(432000, pixel_rate); + + return pixel_rate; +} + /* compute the max rate for new configuration */ static int ilk_max_pixel_rate(struct drm_atomic_state *state) { @@ -10285,9 +10306,9 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state) pixel_rate = ilk_pipe_pixel_rate(crtc_state); - /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ - if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) - pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); + if (IS_BROADWELL(dev_priv)) + pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state, + pixel_rate); intel_state->min_pixclk[i] = pixel_rate; } -- 2.7.4 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v3 2/2] drm/i915/dp: BDW cdclk fix for DP audio 2016-10-25 23:41 ` [PATCH v3 2/2] drm/i915/dp: BDW cdclk fix for DP audio Dhinakaran Pandiyan @ 2016-10-26 8:54 ` Jani Nikula 2016-10-26 18:21 ` Pandiyan, Dhinakaran 0 siblings, 1 reply; 5+ messages in thread From: Jani Nikula @ 2016-10-26 8:54 UTC (permalink / raw) To: Dhinakaran Pandiyan, intel-gfx; +Cc: ville.syrjala, Dhinakaran Pandiyan, stable On Wed, 26 Oct 2016, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> wrote: > According to BSpec, cdclk has to be not less than 432 MHz with DP audio > enabled, port width x4, and link rate HBR2 (5.4 GHz) > > Having a lower cdclk triggers pipe underruns, which then lead to displays > continuously cycling off and on. This is essential for DP MST audio as the > link is trained at HBR2 and 4 lanes by default. > > v3: Combine BDW pixel rate adjustments into a function (Jani) > v2: Restrict fix to BDW > Retain the set cdclk across modesets (Ville) > Cc: stable@vger.kernel.org > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> We'll need this fix for Skylake too, don't we? Maybe Kabylake? Please send a follow-up patch for Skylake with the changes mentioned inline below. BR, Jani. > --- > drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++++++++++++++--- > 1 file changed, 24 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index a94f7d1..efe46b4 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -10260,6 +10260,27 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) > bxt_set_cdclk(to_i915(dev), req_cdclk); > } > > +static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, > + int pixel_rate) > +{ > + /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ > + if (crtc_state->ips_enabled) if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) > + pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); > + > + /* BSpec says "Do not use DisplayPort with CDCLK less than > + * 432 MHz, audio enabled, port width x4, and link rate > + * HBR2 (5.4 GHz), or else there may be audio corruption or > + * screen corruption." > + */ > + if (intel_crtc_has_dp_encoder(crtc_state) && > + crtc_state->has_audio && > + crtc_state->port_clock >= 540000 && > + crtc_state->lane_count == 4) > + pixel_rate = max(432000, pixel_rate); > + > + return pixel_rate; > +} > + > /* compute the max rate for new configuration */ > static int ilk_max_pixel_rate(struct drm_atomic_state *state) > { > @@ -10285,9 +10306,9 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state) > > pixel_rate = ilk_pipe_pixel_rate(crtc_state); > > - /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ > - if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) > - pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); > + if (IS_BROADWELL(dev_priv)) if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv)) > + pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state, > + pixel_rate); > > intel_state->min_pixclk[i] = pixel_rate; > } -- Jani Nikula, Intel Open Source Technology Center ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v3 2/2] drm/i915/dp: BDW cdclk fix for DP audio 2016-10-26 8:54 ` Jani Nikula @ 2016-10-26 18:21 ` Pandiyan, Dhinakaran 2016-10-26 19:08 ` Jani Nikula 0 siblings, 1 reply; 5+ messages in thread From: Pandiyan, Dhinakaran @ 2016-10-26 18:21 UTC (permalink / raw) To: Nikula, Jani Cc: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org, stable@vger.kernel.org On Wed, 2016-10-26 at 11:54 +0300, Jani Nikula wrote: > On Wed, 26 Oct 2016, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> wrote: > > According to BSpec, cdclk has to be not less than 432 MHz with DP audio > > enabled, port width x4, and link rate HBR2 (5.4 GHz) > > > > Having a lower cdclk triggers pipe underruns, which then lead to displays > > continuously cycling off and on. This is essential for DP MST audio as the > > link is trained at HBR2 and 4 lanes by default. > > > > v3: Combine BDW pixel rate adjustments into a function (Jani) > > v2: Restrict fix to BDW > > Retain the set cdclk across modesets (Ville) > > Cc: stable@vger.kernel.org > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Reviewed-by: Jani Nikula <jani.nikula@intel.com> > > We'll need this fix for Skylake too, don't we? Maybe Kabylake? Please > send a follow-up patch for Skylake with the changes mentioned inline > below. > > BR, > Jani. > > Patch 1/2 should take care of gen9 platforms when audio sampling rates are <= 96 kHz. I am still not sure how to increase increase cdclk when the sampling rates > 96kHZ , that is why I have added the TODO in Patch 1/2. > > --- > > drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++++++++++++++--- > > 1 file changed, 24 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > index a94f7d1..efe46b4 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -10260,6 +10260,27 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) > > bxt_set_cdclk(to_i915(dev), req_cdclk); > > } > > > > +static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, > > + int pixel_rate) > > +{ > > + /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ > > + if (crtc_state->ips_enabled) > > if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) > > > + pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); > > + > > + /* BSpec says "Do not use DisplayPort with CDCLK less than > > + * 432 MHz, audio enabled, port width x4, and link rate > > + * HBR2 (5.4 GHz), or else there may be audio corruption or > > + * screen corruption." > > + */ > > + if (intel_crtc_has_dp_encoder(crtc_state) && > > + crtc_state->has_audio && > > + crtc_state->port_clock >= 540000 && > > + crtc_state->lane_count == 4) > > + pixel_rate = max(432000, pixel_rate); > > + > > + return pixel_rate; > > +} > > + > > /* compute the max rate for new configuration */ > > static int ilk_max_pixel_rate(struct drm_atomic_state *state) > > { > > @@ -10285,9 +10306,9 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state) > > > > pixel_rate = ilk_pipe_pixel_rate(crtc_state); > > > > - /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ > > - if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) > > - pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); > > + if (IS_BROADWELL(dev_priv)) > > if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv)) > > > + pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state, > > + pixel_rate); > > > > intel_state->min_pixclk[i] = pixel_rate; > > } > ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v3 2/2] drm/i915/dp: BDW cdclk fix for DP audio 2016-10-26 18:21 ` Pandiyan, Dhinakaran @ 2016-10-26 19:08 ` Jani Nikula 2016-10-26 20:29 ` [Intel-gfx] " Pandiyan, Dhinakaran 0 siblings, 1 reply; 5+ messages in thread From: Jani Nikula @ 2016-10-26 19:08 UTC (permalink / raw) To: Pandiyan, Dhinakaran Cc: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org, stable@vger.kernel.org On Wed, 26 Oct 2016, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com> wrote: > On Wed, 2016-10-26 at 11:54 +0300, Jani Nikula wrote: >> On Wed, 26 Oct 2016, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> wrote: >> > According to BSpec, cdclk has to be not less than 432 MHz with DP audio >> > enabled, port width x4, and link rate HBR2 (5.4 GHz) >> > >> > Having a lower cdclk triggers pipe underruns, which then lead to displays >> > continuously cycling off and on. This is essential for DP MST audio as the >> > link is trained at HBR2 and 4 lanes by default. >> > >> > v3: Combine BDW pixel rate adjustments into a function (Jani) >> > v2: Restrict fix to BDW >> > Retain the set cdclk across modesets (Ville) >> > Cc: stable@vger.kernel.org >> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> >> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> >> >> Reviewed-by: Jani Nikula <jani.nikula@intel.com> >> >> We'll need this fix for Skylake too, don't we? Maybe Kabylake? Please >> send a follow-up patch for Skylake with the changes mentioned inline >> below. >> >> BR, >> Jani. >> >> > > Patch 1/2 should take care of gen9 platforms when audio sampling rates > are <= 96 kHz. I am still not sure how to increase increase cdclk when > the sampling rates > 96kHZ , that is why I have added the TODO in Patch > 1/2. IIUC the two patches and fixes are related, but separate. This one requires 4 lanes, the other one doesn't. For this one there's no mention of audio sampling rate. BR, Jani. > >> > --- >> > drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++++++++++++++--- >> > 1 file changed, 24 insertions(+), 3 deletions(-) >> > >> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c >> > index a94f7d1..efe46b4 100644 >> > --- a/drivers/gpu/drm/i915/intel_display.c >> > +++ b/drivers/gpu/drm/i915/intel_display.c >> > @@ -10260,6 +10260,27 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) >> > bxt_set_cdclk(to_i915(dev), req_cdclk); >> > } >> > >> > +static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, >> > + int pixel_rate) >> > +{ >> > + /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ >> > + if (crtc_state->ips_enabled) >> >> if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) >> >> > + pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); >> > + >> > + /* BSpec says "Do not use DisplayPort with CDCLK less than >> > + * 432 MHz, audio enabled, port width x4, and link rate >> > + * HBR2 (5.4 GHz), or else there may be audio corruption or >> > + * screen corruption." >> > + */ >> > + if (intel_crtc_has_dp_encoder(crtc_state) && >> > + crtc_state->has_audio && >> > + crtc_state->port_clock >= 540000 && >> > + crtc_state->lane_count == 4) >> > + pixel_rate = max(432000, pixel_rate); >> > + >> > + return pixel_rate; >> > +} >> > + >> > /* compute the max rate for new configuration */ >> > static int ilk_max_pixel_rate(struct drm_atomic_state *state) >> > { >> > @@ -10285,9 +10306,9 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state) >> > >> > pixel_rate = ilk_pipe_pixel_rate(crtc_state); >> > >> > - /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ >> > - if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) >> > - pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); >> > + if (IS_BROADWELL(dev_priv)) >> >> if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv)) >> >> > + pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state, >> > + pixel_rate); >> > >> > intel_state->min_pixclk[i] = pixel_rate; >> > } >> > -- Jani Nikula, Intel Open Source Technology Center ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH v3 2/2] drm/i915/dp: BDW cdclk fix for DP audio 2016-10-26 19:08 ` Jani Nikula @ 2016-10-26 20:29 ` Pandiyan, Dhinakaran 0 siblings, 0 replies; 5+ messages in thread From: Pandiyan, Dhinakaran @ 2016-10-26 20:29 UTC (permalink / raw) To: Nikula, Jani Cc: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org, stable@vger.kernel.org On Wed, 2016-10-26 at 22:08 +0300, Jani Nikula wrote: > On Wed, 26 Oct 2016, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com> wrote: > > On Wed, 2016-10-26 at 11:54 +0300, Jani Nikula wrote: > >> On Wed, 26 Oct 2016, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> wrote: > >> > According to BSpec, cdclk has to be not less than 432 MHz with DP audio > >> > enabled, port width x4, and link rate HBR2 (5.4 GHz) > >> > > >> > Having a lower cdclk triggers pipe underruns, which then lead to displays > >> > continuously cycling off and on. This is essential for DP MST audio as the > >> > link is trained at HBR2 and 4 lanes by default. > >> > > >> > v3: Combine BDW pixel rate adjustments into a function (Jani) > >> > v2: Restrict fix to BDW > >> > Retain the set cdclk across modesets (Ville) > >> > Cc: stable@vger.kernel.org > >> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > >> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > >> > >> Reviewed-by: Jani Nikula <jani.nikula@intel.com> > >> > >> We'll need this fix for Skylake too, don't we? Maybe Kabylake? Please > >> send a follow-up patch for Skylake with the changes mentioned inline > >> below. > >> > >> BR, > >> Jani. > >> > >> > > > > Patch 1/2 should take care of gen9 platforms when audio sampling rates > > are <= 96 kHz. I am still not sure how to increase increase cdclk when > > the sampling rates > 96kHZ , that is why I have added the TODO in Patch > > 1/2. > > IIUC the two patches and fixes are related, but separate. This one > requires 4 lanes, the other one doesn't. For this one there's no mention > of audio sampling rate. > > BR, > Jani. > > That's right, this one is needed on BDW for DP HBR2, 4 lanes irrespective of the audio sampling rate. Here's the relevant description that I found in BSpec for this patch. [Register] DP_TP_CTL Project BDW, SKL:*:A, SKL:*:B, SKL:*:C, SKL:*:D, BXT:*:A Do not use DisplayPort with CDCLK less than 432 MHz, audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else there may be audio corruption or screen corruption. -DK > > > >> > --- > >> > drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++++++++++++++--- > >> > 1 file changed, 24 insertions(+), 3 deletions(-) > >> > > >> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > >> > index a94f7d1..efe46b4 100644 > >> > --- a/drivers/gpu/drm/i915/intel_display.c > >> > +++ b/drivers/gpu/drm/i915/intel_display.c > >> > @@ -10260,6 +10260,27 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) > >> > bxt_set_cdclk(to_i915(dev), req_cdclk); > >> > } > >> > > >> > +static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, > >> > + int pixel_rate) > >> > +{ > >> > + /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ > >> > + if (crtc_state->ips_enabled) > >> > >> if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) > >> > >> > + pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); > >> > + > >> > + /* BSpec says "Do not use DisplayPort with CDCLK less than > >> > + * 432 MHz, audio enabled, port width x4, and link rate > >> > + * HBR2 (5.4 GHz), or else there may be audio corruption or > >> > + * screen corruption." > >> > + */ > >> > + if (intel_crtc_has_dp_encoder(crtc_state) && > >> > + crtc_state->has_audio && > >> > + crtc_state->port_clock >= 540000 && > >> > + crtc_state->lane_count == 4) > >> > + pixel_rate = max(432000, pixel_rate); > >> > + > >> > + return pixel_rate; > >> > +} > >> > + > >> > /* compute the max rate for new configuration */ > >> > static int ilk_max_pixel_rate(struct drm_atomic_state *state) > >> > { > >> > @@ -10285,9 +10306,9 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state) > >> > > >> > pixel_rate = ilk_pipe_pixel_rate(crtc_state); > >> > > >> > - /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ > >> > - if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) > >> > - pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); > >> > + if (IS_BROADWELL(dev_priv)) > >> > >> if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv)) > >> > >> > + pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state, > >> > + pixel_rate); > >> > > >> > intel_state->min_pixclk[i] = pixel_rate; > >> > } > >> > > > ^ permalink raw reply [flat|nested] 5+ messages in thread
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2016-10-25 23:41 ` [PATCH v3 2/2] drm/i915/dp: BDW cdclk fix for DP audio Dhinakaran Pandiyan
2016-10-26 8:54 ` Jani Nikula
2016-10-26 18:21 ` Pandiyan, Dhinakaran
2016-10-26 19:08 ` Jani Nikula
2016-10-26 20:29 ` [Intel-gfx] " Pandiyan, Dhinakaran
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