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[156.67.96.201]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abb98ed07afsm568376866b.102.2025.02.19.00.59.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 19 Feb 2025 00:59:06 -0800 (PST) Message-ID: <96738386-9155-4eea-b91d-8590ef3b4562@gmail.com> Date: Wed, 19 Feb 2025 09:59:05 +0100 Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 6.13 116/274] drm/amdgpu/gfx9: manually control gfxoff for CS on RV To: Greg Kroah-Hartman , stable@vger.kernel.org Cc: patches@lists.linux.dev, Lijo Lazar , Sergey Kovalenko , Alex Deucher References: <20250219082609.533585153@linuxfoundation.org> <20250219082614.161530240@linuxfoundation.org> Content-Language: en-US, pl-PL From: =?UTF-8?B?QsWCYcW8ZWogU3pjenlnaWXFgg==?= In-Reply-To: <20250219082614.161530240@linuxfoundation.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit This patch has to be changed for 6.13 - "gfx_v9_0_set_powergating_state" has 'amdgpu_device' argument instead of 'amdgpu_ip_block' argument there. On 2/19/25 09:26, Greg Kroah-Hartman wrote: > 6.13-stable review patch. If anyone has any objections, please let me know. > > ------------------ > > From: Alex Deucher > > commit b35eb9128ebeec534eed1cefd6b9b1b7282cf5ba upstream. > > When mesa started using compute queues more often > we started seeing additional hangs with compute queues. > Disabling gfxoff seems to mitigate that. Manually > control gfxoff and gfx pg with command submissions to avoid > any issues related to gfxoff. KFD already does the same > thing for these chips. > > v2: limit to compute > v3: limit to APUs > v4: limit to Raven/PCO > v5: only update the compute ring_funcs > v6: Disable GFX PG > v7: adjust order > > Reviewed-by: Lijo Lazar > Suggested-by: Błażej Szczygieł > Suggested-by: Sergey Kovalenko > Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3861 > Link: https://lists.freedesktop.org/archives/amd-gfx/2025-January/119116.html > Signed-off-by: Alex Deucher > Cc: stable@vger.kernel.org # 6.12.x > Signed-off-by: Greg Kroah-Hartman > --- > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 36 ++++++++++++++++++++++++++++++++-- > 1 file changed, 34 insertions(+), 2 deletions(-) > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > @@ -7439,6 +7439,38 @@ static void gfx_v9_0_ring_emit_cleaner_s > amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ > } > > +static void gfx_v9_0_ring_begin_use_compute(struct amdgpu_ring *ring) > +{ > + struct amdgpu_device *adev = ring->adev; > + struct amdgpu_ip_block *gfx_block = > + amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); > + > + amdgpu_gfx_enforce_isolation_ring_begin_use(ring); > + > + /* Raven and PCO APUs seem to have stability issues > + * with compute and gfxoff and gfx pg. Disable gfx pg during > + * submission and allow again afterwards. > + */ > + if (gfx_block && amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 1, 0)) > + gfx_v9_0_set_powergating_state(gfx_block, AMD_PG_STATE_UNGATE); > +} > + > +static void gfx_v9_0_ring_end_use_compute(struct amdgpu_ring *ring) > +{ > + struct amdgpu_device *adev = ring->adev; > + struct amdgpu_ip_block *gfx_block = > + amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); > + > + /* Raven and PCO APUs seem to have stability issues > + * with compute and gfxoff and gfx pg. Disable gfx pg during > + * submission and allow again afterwards. > + */ > + if (gfx_block && amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 1, 0)) > + gfx_v9_0_set_powergating_state(gfx_block, AMD_PG_STATE_GATE); > + > + amdgpu_gfx_enforce_isolation_ring_end_use(ring); > +} > + > static const struct amd_ip_funcs gfx_v9_0_ip_funcs = { > .name = "gfx_v9_0", > .early_init = gfx_v9_0_early_init, > @@ -7615,8 +7647,8 @@ static const struct amdgpu_ring_funcs gf > .emit_wave_limit = gfx_v9_0_emit_wave_limit, > .reset = gfx_v9_0_reset_kcq, > .emit_cleaner_shader = gfx_v9_0_ring_emit_cleaner_shader, > - .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, > - .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, > + .begin_use = gfx_v9_0_ring_begin_use_compute, > + .end_use = gfx_v9_0_ring_end_use_compute, > }; > > static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { > >