From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E4E6604A9 for ; Tue, 20 Feb 2024 11:15:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708427722; cv=none; b=HsMyvONTVDH7X6kCQaHF5+l3tMFJ5Dgs3SpW12cjUsYWg2oIHbpd6nHlb2/AIaV274/KSJW8KRFn0K+0gy1KOzPIIaQkTHvndf8mJfP5mdtOTG4jjmHe+1JJMI9gbwlaaW1Q3tiawaMn/YLJJP2YAYG/w0M27xgc7VSVtGO8lpo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708427722; c=relaxed/simple; bh=4VpxTVVljrd5O5tk4aKFQR+l73LULNECbhvrEuohrH8=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=G27BlpPCMBcn0v1WbGbkxh9yGw+Y2OqbWRhw2+KI/7acTlednWIG9yKMyromhzkN9DRftL5ero3S1hnKx0iqo78cY5mJoH+Uwf06GjwoVCownZZye6tCoAjw7V7v2qCAizcdbsrPOpSOQoGPf1DUwm98V61GlGmZcAM6QG12plk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=j++qa4dP; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="j++qa4dP" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1708427720; x=1739963720; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=4VpxTVVljrd5O5tk4aKFQR+l73LULNECbhvrEuohrH8=; b=j++qa4dPTx1uPUBGzr+viR0dgVdl+Y7PFHICu6uiS578krVXSect2avW NTG88yGrBLBlo3ZcfxxSCo/pmitID/aUGFkEh9IwydHywBfKO099OuQjJ a945Rk/cypRY3O+YD3m5JyrYOz0aQTV0bcOlk2IOQiE7KBY8OXhCSNNJs 53Ao7p0Sd0ZGXXI6gl80Gi++Fc1aQ5cuv2ICTqN7yPwuBD9IItWq1GVA+ +QsnPhrTG1xW+UZrn198zF4LCHVEMUV+HyA/SZDpYIXWe0GU5nQgUqtKZ 9DpQue3RBm4XXtbDLja+bMDjPOhZwdwE83xnZXQ4ac3PHHwMgNs7SNURM Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10989"; a="20055959" X-IronPort-AV: E=Sophos;i="6.06,172,1705392000"; d="scan'208";a="20055959" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2024 03:15:16 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,172,1705392000"; d="scan'208";a="35774805" Received: from dunnejor-mobl2.ger.corp.intel.com (HELO [10.213.231.185]) ([10.213.231.185]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2024 03:15:15 -0800 Message-ID: <97b11121-4c48-4dd9-b966-4c42eda3f6a3@linux.intel.com> Date: Tue, 20 Feb 2024 11:15:05 +0000 Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] drm/i915/gt: Set default CCS mode '1' To: Andi Shyti Cc: intel-gfx , dri-devel , Chris Wilson , Joonas Lahtinen , Matt Roper , stable@vger.kernel.org, Andi Shyti References: <20240215135924.51705-1-andi.shyti@linux.intel.com> <20240215135924.51705-3-andi.shyti@linux.intel.com> Content-Language: en-US From: Tvrtko Ursulin Organization: Intel Corporation UK Plc In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 20/02/2024 10:11, Andi Shyti wrote: > Hi Tvrtko, > > On Mon, Feb 19, 2024 at 12:51:44PM +0000, Tvrtko Ursulin wrote: >> On 19/02/2024 11:16, Tvrtko Ursulin wrote: >>> On 15/02/2024 13:59, Andi Shyti wrote: > > ... > >>>> +/* >>>> + * Exclude unavailable engines. >>>> + * >>>> + * Only the first CCS engine is utilized due to the disabling of >>>> CCS auto load >>>> + * balancing. As a result, all CCS engines operate collectively, >>>> functioning >>>> + * essentially as a single CCS engine, hence the count of active >>>> CCS engines is >>>> + * considered '1'. >>>> + * Currently, this applies to platforms with more than one CCS engine, >>>> + * specifically DG2. >>>> + */ >>>> +#define for_each_available_uabi_engine(engine__, i915__) \ >>>> +    for_each_uabi_engine(engine__, i915__) \ >>>> +        if ((IS_DG2(i915__)) && \ >>>> +            ((engine__)->uabi_class == I915_ENGINE_CLASS_COMPUTE) && \ >>>> +            ((engine__)->uabi_instance)) { } \ >>>> +        else >>>> + >>> >>> If you don't want userspace to see some engines, just don't add them to >>> the uabi list in intel_engines_driver_register or thereabouts? > > It will be dynamic. In next series I am preparing the user will > be able to increase the number of CCS engines he wants to use. Oh tricky and new. Does it need to be at runtime or could be boot time? If you are aiming to make the static single CCS only into the 6.9 release, and you feel running out of time, you could always do a simple solution for now. The one I mentioned of simply not registering on the uabi list. Then you can refine more leisurely for the next release. Regards, Tvrtko > >>> Similar as we do for gsc which uses I915_NO_UABI_CLASS, although for ccs >>> you can choose a different approach, whatever is more elegant. >>> >>> That is also needed for i915->engine_uabi_class_count to be right, so >>> userspace stats which rely on it are correct. > > Oh yes. Will update it. > >> I later realized it is more than that - everything that uses >> intel_engine_lookup_user to look up class instance passed in from userspace >> relies on the engine not being on the user list otherwise userspace could >> bypass the fact engine query does not list it. Like PMU, Perf/POA, context >> engine map and SSEU context query. > > Correct, will look into that, thank you! > > Andi