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Tue, 17 Mar 2026 09:44:41 -0700 (PDT) Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20260317163006.959177102@linuxfoundation.org> <20260317163008.013706115@linuxfoundation.org> In-Reply-To: <20260317163008.013706115@linuxfoundation.org> From: Pengyu Luo Date: Wed, 18 Mar 2026 00:44:16 +0800 X-Gm-Features: AaiRm524OytN7slxZeciId_g8UhvL034v3qBbAQcxH7-KpElWSyfYcpzgxFm_6I Message-ID: Subject: Re: [PATCH 6.19 028/378] drm/msm/dsi: fix hdisplay calculation when programming dsi registers To: Greg Kroah-Hartman Cc: stable@vger.kernel.org, patches@lists.linux.dev, Dmitry Baryshkov , Sasha Levin Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, Mar 18, 2026 at 12:40=E2=80=AFAM Greg Kroah-Hartman wrote: > > 6.19-stable review patch. If anyone has any objections, please let me kn= ow. > > ------------------ > > From: Pengyu Luo > > [ Upstream commit ac47870fd795549f03d57e0879fc730c79119f4b ] > > Recently, the hdisplay calculation is working for 3:1 compressed ratio > only. If we have a video panel with DSC BPP =3D 8, and BPC =3D 10, we sti= ll > use the default bits_per_pclk =3D 24, then we get the wrong hdisplay. We > can draw the conclusion by cross-comparing the calculation with the > calculation in dsi_adjust_pclk_for_compression(). > > Since CMD mode does not use this, we can remove > !(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) safely. > > Fixes: efcbd6f9cdeb ("drm/msm/dsi: Enable widebus for DSI") > Signed-off-by: Pengyu Luo > Reviewed-by: Dmitry Baryshkov > Patchwork: https://patchwork.freedesktop.org/patch/704822/ > Link: https://lore.kernel.org/r/20260214105145.105308-1-mitltlatltl@gmail= .com > Signed-off-by: Dmitry Baryshkov > Signed-off-by: Sasha Levin > --- Hi, Greg. You just told me you dropped it. Please drop this patch for all stable trees. Best wishes, Pengyu > drivers/gpu/drm/msm/dsi/dsi_host.c | 14 ++++++++------ > 1 file changed, 8 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi= /dsi_host.c > index e0de545d40775..e8e83ee61eb09 100644 > --- a/drivers/gpu/drm/msm/dsi/dsi_host.c > +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c > @@ -993,7 +993,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm= _host, bool is_bonded_dsi) > > if (msm_host->dsc) { > struct drm_dsc_config *dsc =3D msm_host->dsc; > - u32 bytes_per_pclk; > + u32 bits_per_pclk; > > /* update dsc params with timing params */ > if (!dsc || !mode->hdisplay || !mode->vdisplay) { > @@ -1015,7 +1015,9 @@ static void dsi_timing_setup(struct msm_dsi_host *m= sm_host, bool is_bonded_dsi) > > /* > * DPU sends 3 bytes per pclk cycle to DSI. If widebus is > - * enabled, bus width is extended to 6 bytes. > + * enabled, MDP always sends out 48-bit compressed data p= er > + * pclk and on average, DSI consumes an amount of compres= sed > + * data equivalent to the uncompressed pixel depth per pc= lk. > * > * Calculate the number of pclks needed to transmit one l= ine of > * the compressed data. > @@ -1027,12 +1029,12 @@ static void dsi_timing_setup(struct msm_dsi_host = *msm_host, bool is_bonded_dsi) > * unused anyway. > */ > h_total -=3D hdisplay; > - if (wide_bus_enabled && !(msm_host->mode_flags & MIPI_DSI= _MODE_VIDEO)) > - bytes_per_pclk =3D 6; > + if (wide_bus_enabled) > + bits_per_pclk =3D mipi_dsi_pixel_format_to_bpp(ms= m_host->format); > else > - bytes_per_pclk =3D 3; > + bits_per_pclk =3D 24; > > - hdisplay =3D DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_= host->dsc), bytes_per_pclk); > + hdisplay =3D DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_= host->dsc) * 8, bits_per_pclk); > > h_total +=3D hdisplay; > ha_end =3D ha_start + hdisplay; > -- > 2.51.0 > > >