From: Paul Grandperrin <paul.grandperrin@gmail.com>
To: Ricky WU <ricky_wu@realtek.com>
Cc: Greg KH <gregkh@linuxfoundation.org>,
Linux regressions mailing list <regressions@lists.linux.dev>,
stable@vger.kernel.org, Wei_wang <wei_wang@realsil.com.cn>,
Roger Tseng <rogerable@realtek.com>,
Linus Torvalds <torvalds@linux-foundation.org>
Subject: RE: Regression since 6.1.46 (commit 8ee39ec): rtsx_pci from drivers/misc/cardreader breaks NVME power state, preventing system boot
Date: Wed, 20 Sep 2023 11:33:51 +0200 [thread overview]
Message-ID: <FK2A1S.OMEJ59SJW1RG3@gmail.com> (raw)
In-Reply-To: <995632624f0e4d26b73fb934a8eeaebc@realtek.com>
Hi Ricky,
I'm going to test it right now! Thanks!
On Wed, Sep 20 2023 at 07:30:00 +00:00:00, Ricky WU
<ricky_wu@realtek.com> wrote:
> Hi Greg k-h,
>
> This patch is our solution for this issue...
> And now how can I push this?
>
> Hi Paul，
>
> Can you help to try this patch? Is it work for your platform?
>
> Ricky
>
>
> ---
> drivers/misc/cardreader/rts5227.c | 55 ++++------------------------
> drivers/misc/cardreader/rts5228.c | 57
> +++++++++---------------------
> drivers/misc/cardreader/rts5249.c | 56 ++++-------------------------
> drivers/misc/cardreader/rts5260.c | 43 +++++++---------------
> drivers/misc/cardreader/rts5261.c | 52 +++++++--------------------
> drivers/misc/cardreader/rtsx_pcr.c | 51 +++++++++++++++++++++++---
> 6 files changed, 102 insertions(+), 212 deletions(-)
>
> diff --git a/drivers/misc/cardreader/rts5227.c
> b/drivers/misc/cardreader/rts5227.c
> index 3dae5e3a1697..cd512284bfb3 100644
> --- a/drivers/misc/cardreader/rts5227.c
> +++ b/drivers/misc/cardreader/rts5227.c
> @@ -83,63 +83,20 @@ static void rts5227_fetch_vendor_settings(struct
> rtsx_pcr *pcr)
>
> static void rts5227_init_from_cfg(struct rtsx_pcr *pcr)
> {
> - struct pci_dev *pdev = pcr->pci;
> - int l1ss;
> - u32 lval;
> struct rtsx_cr_option *option = &pcr->option;
>
> - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
> - if (!l1ss)
> - return;
> -
> - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
> -
> if (CHK_PCI_PID(pcr, 0x522A)) {
> - if (0 == (lval & 0x0F))
> - rtsx_pci_enable_oobs_polling(pcr);
> - else
> + if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
> + | PM_L1_1_EN | PM_L1_2_EN))
> rtsx_pci_disable_oobs_polling(pcr);
> + else
> + rtsx_pci_enable_oobs_polling(pcr);
> }
>
> - if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
> - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
> - else
> - rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
> -
> - if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
> - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
> - else
> - rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
> -
> - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
> - rtsx_set_dev_flag(pcr, PM_L1_1_EN);
> - else
> - rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
> -
> - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
> - rtsx_set_dev_flag(pcr, PM_L1_2_EN);
> - else
> - rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
> -
> if (option->ltr_en) {
> - u16 val;
> -
> - pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
> - if (val & PCI_EXP_DEVCTL2_LTR_EN) {
> - option->ltr_enabled = true;
> - option->ltr_active = true;
> + if (option->ltr_enabled)
> rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
> - } else {
> - option->ltr_enabled = false;
> - }
> }
> -
> - if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
> - | PM_L1_1_EN | PM_L1_2_EN))
> - option->force_clkreq_0 = false;
> - else
> - option->force_clkreq_0 = true;
> -
> }
>
> static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
> @@ -195,7 +152,7 @@ static int rts5227_extra_init_hw(struct rtsx_pcr
> *pcr)
> }
> }
>
> - if (option->force_clkreq_0 && pcr->aspm_mode == ASPM_MODE_CFG)
> + if (option->force_clkreq_0)
> rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
> FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
> else
> diff --git a/drivers/misc/cardreader/rts5228.c
> b/drivers/misc/cardreader/rts5228.c
> index f4ab09439da7..0c7f10bcf6f1 100644
> --- a/drivers/misc/cardreader/rts5228.c
> +++ b/drivers/misc/cardreader/rts5228.c
> @@ -386,59 +386,25 @@ static void rts5228_process_ocp(struct rtsx_pcr
> *pcr)
>
> static void rts5228_init_from_cfg(struct rtsx_pcr *pcr)
> {
> - struct pci_dev *pdev = pcr->pci;
> - int l1ss;
> - u32 lval;
> struct rtsx_cr_option *option = &pcr->option;
>
> - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
> - if (!l1ss)
> - return;
> -
> - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
> -
> - if (0 == (lval & 0x0F))
> - rtsx_pci_enable_oobs_polling(pcr);
> - else
> + if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
> + | PM_L1_1_EN | PM_L1_2_EN))
> rtsx_pci_disable_oobs_polling(pcr);
> -
> - if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
> - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
> - else
> - rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
> -
> - if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
> - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
> - else
> - rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
> -
> - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
> - rtsx_set_dev_flag(pcr, PM_L1_1_EN);
> else
> - rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
> -
> - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
> - rtsx_set_dev_flag(pcr, PM_L1_2_EN);
> - else
> - rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
> + rtsx_pci_enable_oobs_polling(pcr);
>
> rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
> - if (option->ltr_en) {
> - u16 val;
>
> - pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
> - if (val & PCI_EXP_DEVCTL2_LTR_EN) {
> - option->ltr_enabled = true;
> - option->ltr_active = true;
> + if (option->ltr_en) {
> + if (option->ltr_enabled)
> rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
> - } else {
> - option->ltr_enabled = false;
> - }
> }
> }
>
> static int rts5228_extra_init_hw(struct rtsx_pcr *pcr)
> {
> + struct rtsx_cr_option *option = &pcr->option;
>
> rtsx_pci_write_register(pcr, RTS5228_AUTOLOAD_CFG1,
> CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);
> @@ -469,6 +435,17 @@ static int rts5228_extra_init_hw(struct rtsx_pcr
> *pcr)
> else
> rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);
>
> + /*
> + * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
> + * to drive low, and we forcibly request clock.
> + */
> + if (option->force_clkreq_0)
> + rtsx_pci_write_register(pcr, PETXCFG,
> + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
> + else
> + rtsx_pci_write_register(pcr, PETXCFG,
> + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
> +
> rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB);
>
> if (pcr->rtd3_en) {
> diff --git a/drivers/misc/cardreader/rts5249.c
> b/drivers/misc/cardreader/rts5249.c
> index 47ab72a43256..6c81040e18be 100644
> --- a/drivers/misc/cardreader/rts5249.c
> +++ b/drivers/misc/cardreader/rts5249.c
> @@ -86,64 +86,22 @@ static void
> rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
>
> static void rts5249_init_from_cfg(struct rtsx_pcr *pcr)
> {
> - struct pci_dev *pdev = pcr->pci;
> - int l1ss;
> struct rtsx_cr_option *option = &(pcr->option);
> - u32 lval;
> -
> - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
> - if (!l1ss)
> - return;
> -
> - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
>
> if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
> - if (0 == (lval & 0x0F))
> - rtsx_pci_enable_oobs_polling(pcr);
> - else
> + if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
> + | PM_L1_1_EN | PM_L1_2_EN))
> rtsx_pci_disable_oobs_polling(pcr);
> + else
> + rtsx_pci_enable_oobs_polling(pcr);
> }
>
> -
> - if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
> - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
> -
> - if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
> - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
> -
> - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
> - rtsx_set_dev_flag(pcr, PM_L1_1_EN);
> -
> - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
> - rtsx_set_dev_flag(pcr, PM_L1_2_EN);
> -
> if (option->ltr_en) {
> - u16 val;
> -
> - pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val);
> - if (val & PCI_EXP_DEVCTL2_LTR_EN) {
> - option->ltr_enabled = true;
> - option->ltr_active = true;
> + if (option->ltr_enabled)
> rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
> - } else {
> - option->ltr_enabled = false;
> - }
> }
> }
>
> -static int rts5249_init_from_hw(struct rtsx_pcr *pcr)
> -{
> - struct rtsx_cr_option *option = &(pcr->option);
> -
> - if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
> - | PM_L1_1_EN | PM_L1_2_EN))
> - option->force_clkreq_0 = false;
> - else
> - option->force_clkreq_0 = true;
> -
> - return 0;
> -}
> -
> static void rts52xa_force_power_down(struct rtsx_pcr *pcr, u8
> pm_state, bool runtime)
> {
> /* Set relink_time to 0 */
> @@ -276,7 +234,6 @@ static int rts5249_extra_init_hw(struct rtsx_pcr
> *pcr)
> struct rtsx_cr_option *option = &(pcr->option);
>
> rts5249_init_from_cfg(pcr);
> - rts5249_init_from_hw(pcr);
>
> rtsx_pci_init_cmd(pcr);
>
> @@ -327,11 +284,12 @@ static int rts5249_extra_init_hw(struct
> rtsx_pcr *pcr)
> }
> }
>
> +
> /*
> * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
> * to drive low, and we forcibly request clock.
> */
> - if (option->force_clkreq_0 && pcr->aspm_mode == ASPM_MODE_CFG)
> + if (option->force_clkreq_0)
> rtsx_pci_write_register(pcr, PETXCFG,
> FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
> else
> diff --git a/drivers/misc/cardreader/rts5260.c
> b/drivers/misc/cardreader/rts5260.c
> index 79b18f6f73a8..d2d3a6ccb8f7 100644
> --- a/drivers/misc/cardreader/rts5260.c
> +++ b/drivers/misc/cardreader/rts5260.c
> @@ -480,47 +480,19 @@ static void rts5260_pwr_saving_setting(struct
> rtsx_pcr *pcr)
>
> static void rts5260_init_from_cfg(struct rtsx_pcr *pcr)
> {
> - struct pci_dev *pdev = pcr->pci;
> - int l1ss;
> struct rtsx_cr_option *option = &pcr->option;
> - u32 lval;
> -
> - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
> - if (!l1ss)
> - return;
> -
> - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
> -
> - if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
> - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
> -
> - if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
> - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
> -
> - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
> - rtsx_set_dev_flag(pcr, PM_L1_1_EN);
> -
> - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
> - rtsx_set_dev_flag(pcr, PM_L1_2_EN);
>
> rts5260_pwr_saving_setting(pcr);
>
> if (option->ltr_en) {
> - u16 val;
> -
> - pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val);
> - if (val & PCI_EXP_DEVCTL2_LTR_EN) {
> - option->ltr_enabled = true;
> - option->ltr_active = true;
> + if (option->ltr_enabled)
> rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
> - } else {
> - option->ltr_enabled = false;
> - }
> }
> }
>
> static int rts5260_extra_init_hw(struct rtsx_pcr *pcr)
> {
> + struct rtsx_cr_option *option = &pcr->option;
>
> /* Set mcu_cnt to 7 to ensure data can be sampled properly */
> rtsx_pci_write_register(pcr, 0xFC03, 0x7F, 0x07);
> @@ -539,6 +511,17 @@ static int rts5260_extra_init_hw(struct rtsx_pcr
> *pcr)
>
> rts5260_init_hw(pcr);
>
> + /*
> + * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
> + * to drive low, and we forcibly request clock.
> + */
> + if (option->force_clkreq_0)
> + rtsx_pci_write_register(pcr, PETXCFG,
> + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
> + else
> + rtsx_pci_write_register(pcr, PETXCFG,
> + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
> +
> rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
>
> return 0;
> diff --git a/drivers/misc/cardreader/rts5261.c
> b/drivers/misc/cardreader/rts5261.c
> index 94af6bf8a25a..67252512a132 100644
> --- a/drivers/misc/cardreader/rts5261.c
> +++ b/drivers/misc/cardreader/rts5261.c
> @@ -454,54 +454,17 @@ static void rts5261_init_from_hw(struct
> rtsx_pcr *pcr)
>
> static void rts5261_init_from_cfg(struct rtsx_pcr *pcr)
> {
> - struct pci_dev *pdev = pcr->pci;
> - int l1ss;
> - u32 lval;
> struct rtsx_cr_option *option = &pcr->option;
>
> - l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
> - if (!l1ss)
> - return;
> -
> - pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
> -
> - if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
> - rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
> - else
> - rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
> -
> - if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
> - rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
> - else
> - rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
> -
> - if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
> - rtsx_set_dev_flag(pcr, PM_L1_1_EN);
> - else
> - rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
> -
> - if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
> - rtsx_set_dev_flag(pcr, PM_L1_2_EN);
> - else
> - rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
> -
> - rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
> if (option->ltr_en) {
> - u16 val;
> -
> - pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val);
> - if (val & PCI_EXP_DEVCTL2_LTR_EN) {
> - option->ltr_enabled = true;
> - option->ltr_active = true;
> + if (option->ltr_enabled)
> rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
> - } else {
> - option->ltr_enabled = false;
> - }
> }
> }
>
> static int rts5261_extra_init_hw(struct rtsx_pcr *pcr)
> {
> + struct rtsx_cr_option *option = &pcr->option;
> u32 val;
>
> rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1,
> @@ -547,6 +510,17 @@ static int rts5261_extra_init_hw(struct rtsx_pcr
> *pcr)
> else
> rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);
>
> + /*
> + * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
> + * to drive low, and we forcibly request clock.
> + */
> + if (option->force_clkreq_0)
> + rtsx_pci_write_register(pcr, PETXCFG,
> + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
> + else
> + rtsx_pci_write_register(pcr, PETXCFG,
> + FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
> +
> rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB);
>
> if (pcr->rtd3_en) {
> diff --git a/drivers/misc/cardreader/rtsx_pcr.c
> b/drivers/misc/cardreader/rtsx_pcr.c
> index a3f4b52bb159..a30751ad3733 100644
> --- a/drivers/misc/cardreader/rtsx_pcr.c
> +++ b/drivers/misc/cardreader/rtsx_pcr.c
> @@ -1326,11 +1326,8 @@ static int rtsx_pci_init_hw(struct rtsx_pcr
> *pcr)
> return err;
> }
>
> - if (pcr->aspm_mode == ASPM_MODE_REG) {
> + if (pcr->aspm_mode == ASPM_MODE_REG)
> rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0x30, 0x30);
> - rtsx_pci_write_register(pcr, PETXCFG,
> - FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
> - }
>
> /* No CD interrupt if probing driver with card inserted.
> * So we need to initialize pcr->card_exist here.
> @@ -1345,7 +1342,9 @@ static int rtsx_pci_init_hw(struct rtsx_pcr
> *pcr)
>
> static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
> {
> - int err;
> + struct rtsx_cr_option *option = &(pcr->option);
> + int err, l1ss;
> + u32 lval;
> u16 cfg_val;
> u8 val;
>
> @@ -1430,6 +1429,48 @@ static int rtsx_pci_init_chip(struct rtsx_pcr
> *pcr)
> pcr->aspm_enabled = true;
> }
>
> + l1ss = pci_find_ext_capability(pcr->pci, PCI_EXT_CAP_ID_L1SS);
> + if (l1ss) {
> + pci_read_config_dword(pcr->pci, l1ss + PCI_L1SS_CTL1, &lval);
> +
> + if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
> + rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
> + else
> + rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
> +
> + if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
> + rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
> + else
> + rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
> +
> + if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
> + rtsx_set_dev_flag(pcr, PM_L1_1_EN);
> + else
> + rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
> +
> + if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
> + rtsx_set_dev_flag(pcr, PM_L1_2_EN);
> + else
> + rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
> +
> + pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cfg_val);
> + if (cfg_val & PCI_EXP_DEVCTL2_LTR_EN) {
> + option->ltr_enabled = true;
> + option->ltr_active = true;
> + } else {
> + option->ltr_enabled = false;
> + }
> +
> + if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
> + | PM_L1_1_EN | PM_L1_2_EN))
> + option->force_clkreq_0 = false;
> + else
> + option->force_clkreq_0 = true;
> + } else {
> + option->ltr_enabled = false;
> + option->force_clkreq_0 = true;
> + }
> +
> if (pcr->ops->fetch_vendor_settings)
> pcr->ops->fetch_vendor_settings(pcr);
>
> --
> 2.25.1
>
>> -----Original Message-----
>> From: Greg KH <gregkh@linuxfoundation.org>
>> Sent: Tuesday, September 19, 2023 3:06 PM
>> To: Ricky WU <ricky_wu@realtek.com>
>> Cc: Linux regressions mailing list <regressions@lists.linux.dev>;
>> Paul
>> Grandperrin <paul.grandperrin@gmail.com>; stable@vger.kernel.org;
>> Wei_wang <wei_wang@realsil.com.cn>; Roger Tseng
>> <rogerable@realtek.com>; Linus Torvalds
>> <torvalds@linux-foundation.org>
>> Subject: Re: Regression since 6.1.46 (commit 8ee39ec): rtsx_pci from
>> drivers/misc/cardreader breaks NVME power state, preventing system
>> boot
>>
>>
>> External mail.
>>
>>
>>
>> On Tue, Sep 19, 2023 at 02:20:53AM +0000, Ricky WU wrote:
>> > Hi Greg k-h，
>> >
>> > In order to cover the those platform Power saving issue, our
>> approach
>> > on new patch will be different from the previous patch
>> (101bd907b4244a726980ee67f95ed9cafab6ff7a).
>> >
>> > So we need used fixed Tag on
>> 101bd907b4244a726980ee67f95ed9cafab6ff7a
>> > or a new patch for this problem?
>>
>> I'm sorry, but I do not understand. I think a new change is needed
>> here, right?
>> Or are you wanting a different commit backported to stable trees?
>> What
>> about Linus's tree now?
>>
>> What exactly should I do here?
>>
>> confused,
>>
>> greg k-h
next prev parent reply other threads:[~2023-09-20 9:34 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-12 12:29 Regression since 6.1.46 (commit 8ee39ec): rtsx_pci from drivers/misc/cardreader breaks NVME power state, preventing system boot Paul Grandperrin
2023-09-12 17:10 ` Linux regression tracking (Thorsten Leemhuis)
2023-09-13 5:03 ` Greg KH
2023-09-19 2:20 ` Ricky WU
2023-09-19 7:06 ` Greg KH
2023-09-20 7:30 ` Ricky WU
2023-09-20 7:34 ` Greg KH
2023-09-20 8:32 ` Ricky WU
2023-09-26 11:23 ` Salvatore Bonaccorso
2023-09-26 11:51 ` Linux regression tracking (Thorsten Leemhuis)
2023-09-20 9:33 ` Paul Grandperrin [this message]
2023-09-13 3:10 ` Ricky WU
2023-09-19 8:04 ` Jade Lovelace
2023-09-19 9:11 ` Ricky WU
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=FK2A1S.OMEJ59SJW1RG3@gmail.com \
--to=paul.grandperrin@gmail.com \
--cc=gregkh@linuxfoundation.org \
--cc=regressions@lists.linux.dev \
--cc=ricky_wu@realtek.com \
--cc=rogerable@realtek.com \
--cc=stable@vger.kernel.org \
--cc=torvalds@linux-foundation.org \
--cc=wei_wang@realsil.com.cn \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).