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From: Greg KH <gregkh@linuxfoundation.org>
To: Dan Williams <dan.j.williams@intel.com>
Cc: linux-cxl@vger.kernel.org, stable@vger.kernel.org,
	dave.hansen@linux.intel.com, linux-mm@kvack.org,
	linux-acpi@vger.kernel.org
Subject: Re: [PATCH 10/18] cxl/region: Fix passthrough-decoder detection
Date: Mon, 6 Feb 2023 06:38:01 +0100	[thread overview]
Message-ID: <Y+CSOeHVLKudN0A6@kroah.com> (raw)
In-Reply-To: <167564540422.847146.13816934143225777888.stgit@dwillia2-xfh.jf.intel.com>

On Sun, Feb 05, 2023 at 05:03:24PM -0800, Dan Williams wrote:
> A passthrough decoder is a decoder that maps only 1 target. It is a
> special case because it does not impose any constraints on the
> interleave-math as compared to a decoder with multiple targets. Extend
> the passthrough case to multi-target-capable decoders that only have one
> target selected. I.e. the current code was only considering passthrough
> *ports* which are only a subset of the potential passthrough decoder
> scenarios.
> 
> Fixes: e4f6dfa9ef75 ("cxl/region: Fix 'distance' calculation with passthrough ports")
> Cc: <stable@vger.kernel.org>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>

If a patch really is a "fix" that needs to go to stable kernels, why is
it commit 10 out of 18?  Why isn't it going to Linus now for inclusion
in 6.2-final?  Does it depend on the 9 earlier patches in this series?

thanks,

greg k-h

  reply	other threads:[~2023-02-06  5:38 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20230208173730uscas1p2af3a9eeb8946dfa607b190c079a49653@uscas1p2.samsung.com>
2023-02-06  1:02 ` [PATCH 00/18] CXL RAM and the 'Soft Reserved' => 'System RAM' default Dan Williams
2023-02-06  1:03   ` [PATCH 10/18] cxl/region: Fix passthrough-decoder detection Dan Williams
2023-02-06  5:38     ` Greg KH [this message]
2023-02-06 17:22       ` Dan Williams
2023-02-07  0:00     ` Dave Jiang
2023-02-08 12:44     ` Jonathan Cameron
2023-02-09 20:28     ` Verma, Vishal L
2023-02-06  5:36   ` [PATCH 00/18] CXL RAM and the 'Soft Reserved' => 'System RAM' default Gregory Price
2023-02-06 16:40     ` Davidlohr Bueso
2023-02-06 18:23       ` Dan Williams
2023-02-06 17:29     ` Dan Williams
2023-02-06 17:18       ` Davidlohr Bueso
2023-02-08 17:37   ` Fan Ni
2023-02-09  4:56     ` Dan Williams
2023-02-13 12:13   ` David Hildenbrand
2023-02-14 18:45     ` Dan Williams
2023-02-14 18:27   ` Gregory Price
2023-02-14 18:39     ` Dan Williams
2023-02-14 19:01       ` Gregory Price
2023-02-14 21:18         ` Jonathan Cameron
2023-02-14 21:51           ` Gregory Price
2023-02-14 21:54             ` Gregory Price
2023-02-15 10:03               ` Jonathan Cameron
2023-02-18  9:47                 ` Gregory Price

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