From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 225ACC433F5 for ; Thu, 9 Sep 2021 15:37:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 053BA61132 for ; Thu, 9 Sep 2021 15:37:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229816AbhIIPic (ORCPT ); Thu, 9 Sep 2021 11:38:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229745AbhIIPib (ORCPT ); Thu, 9 Sep 2021 11:38:31 -0400 Received: from pandora.armlinux.org.uk (pandora.armlinux.org.uk [IPv6:2001:4d48:ad52:32c8:5054:ff:fe00:142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 31933C061574; Thu, 9 Sep 2021 08:37:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=armlinux.org.uk; s=pandora-2019; h=Sender:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=F73x7V3d25UjGf7zf/PPlbbc+cYf+/nqqVeEZWo13SE=; b=Cm6MI7CiUa/dp8wnVLYXEEu18x drH9hdKleBUpv6awCYZzVsWfntCJUQIl1sku82key36p8QR5laJs32LdWmZgBE2SGflBuqw8dqLpv IW53hKQzfvsLdyVlGrRKlclscA7IWhrFgTPihWc2AflEijeC9ZFp6jcMH838BK0NLrrWSldWFrFjC MS7sCTgAlEoDcrB03qSVZ4iLbvq4UDjfff+AFexeS3K+XM+spiFHNy9VOZRkemqmaWGivr8iNfh+p QbIxszILfFhtIgIU7xCENPxOm0VWiR6sTfNUyKSY6lS6zp0+6YRtKDPskXGHsOI9txrHiRcSxEPgr CLoiF+oQ==; Received: from shell.armlinux.org.uk ([fd8f:7570:feb6:1:5054:ff:fe00:4ec]:45018) by pandora.armlinux.org.uk with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mOM6t-0006iP-WB; Thu, 09 Sep 2021 16:37:06 +0100 Received: from linux by shell.armlinux.org.uk with local (Exim 4.94.2) (envelope-from ) id 1mOM6p-0006P9-2l; Thu, 09 Sep 2021 16:37:03 +0100 Date: Thu, 9 Sep 2021 16:37:03 +0100 From: "Russell King (Oracle)" To: Geert Uytterhoeven Cc: Marc Zyngier , Linux ARM , Linux Kernel Mailing List , Will Deacon , Catalin Marinas , Thomas Gleixner , Jason Cooper , Sumit Garg , Valentin Schneider , Florian Fainelli , Gregory Clement , Andrew Lunn , Android Kernel Team , stable , Magnus Damm , Niklas =?iso-8859-1?Q?S=F6derlund?= , Linux-Renesas Subject: Re: [PATCH v2 07/17] irqchip/gic: Atomically update affinity Message-ID: References: <20200624195811.435857-1-maz@kernel.org> <20200624195811.435857-8-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Sender: Russell King (Oracle) Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org On Thu, Sep 09, 2021 at 05:22:01PM +0200, Geert Uytterhoeven wrote: > Despite the ARM Generic Interrupt Controller Architecture Specification > (both version 1.0 and 2.0) stating that the Interrupt Processor Targets > Registers are byte-accessible, the EMMA Mobile EV2 User's Manual > states that the interrupt registers can be accessed via the APB bus, > in 32-bit units. Using byte accesses locks up the system. Fun. Seems someone can't read ARMs documentation. Even the old ARM IHI 0048B.b document I have for the GIC from 2013 states "In addition, the GICD_IPRIORITYRn, GICD_ITARGETSRn, GICD_CPENDSGIRn, and GICD_SPENDSGIRn registers support byte accesses." However, this kind of thing is sadly not uncommon. There's been a similar issue with the PL011 UART driver as well - some platforms require 16-bit accesses instead of normal 32-bit accesses. > Unfortunately I only have remote access to the board showing the > issue. I did check that adding the writeb_relaxed() before the > writel_relaxed() that was used before also causes a lock-up, so the > issue is not an endian mismatch. > Looking at the driver history, these registers have always been > accessed using 32-bit accesses before. As byte accesses lead > indeed to simpler code, I'm wondering if they had been tried before, > and caused issues before? > > Since you said the locking was bogus before, due to the reliance on > the BL_SWITCHER option, I'm not suggesting a plain revert, but I'm > wondering what kind of locking you suggest to use instead? If byte accesses are not going to be workable, then the only answer _is_ a read-modify-write with working locking. -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!