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Date:   Wed, 8 Dec 2021 14:19:05 +0100
From:   Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To:     Patrik John <patrik.john@u-blox.com>
Cc:     stable@vger.kernel.org
Subject: Re: [PATCH] serial: tegra: Change lower tolerance baud rate limit
 for tegra20 and tegra30
Message-ID: <YbCwyVoz4o5wMuXJ@kroah.com>
References: <sig.0974db5058.20211206171457.1639733-1-patrik.john@u-blox.com>
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On Mon, Dec 06, 2021 at 06:14:57PM +0100, Patrik John wrote:
> commit b40de7469ef135161c80af0e8c462298cc5dac00 upstream.
> 
> The current implementation uses 0 as lower limit for the baud rate
> tolerance for tegra20 and tegra30 chips which causes isses on UART
> initialization as soon as baud rate clock is lower than required even
> when within the standard UART tolerance of +/- 4%.
> 
> This fix aligns the implementation with the initial commit description
> of +/- 4% tolerance for tegra chips other than tegra186 and tegra194.
> 
> Fixes: d781ec21bae6 ("serial: tegra: report clk rate errors")
> Cc: stable <stable@vger.kernel.org>
> Signed-off-by: Patrik John <patrik.john@u-blox.com>
> Link: https://lore.kernel.org/r/sig.19614244f8.20211123132737.88341-1-patrik.john@u-blox.com
> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> ---
> Backport for 5.4-stable 

Now queued up, thanks.

greg k-h