* [PATCH] arm64: errata: Add Cortex-A510 to the repeat tlbi list
@ 2022-08-30 15:08 Lucas Wei
2022-08-30 15:13 ` Lucas Wei
2022-08-30 15:22 ` Greg KH
0 siblings, 2 replies; 6+ messages in thread
From: Lucas Wei @ 2022-08-30 15:08 UTC (permalink / raw)
To: stable, gregkh
Cc: lucaswei, robinpeng, willdeacon, aaronding, danielmentz,
James Morse
From: James Morse <james.morse@arm.com>
Cortex-A510 is affected by an erratum where in rare circumstances the
CPUs may not handle a race between a break-before-make sequence on one
CPU, and another CPU accessing the same page. This could allow a store
to a page that has been unmapped.
Work around this by adding the affected CPUs to the list that needs
TLB sequences to be done twice.
Signed-off-by: James Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20220704155732.21216-1-james.morse@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
---
Documentation/arm64/silicon-errata.rst | 2 ++
arch/arm64/Kconfig | 17 +++++++++++++++++
arch/arm64/kernel/cpu_errata.c | 8 +++++++-
3 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
index 0b4235b1f8c4..33b04db8408f 100644
--- a/Documentation/arm64/silicon-errata.rst
+++ b/Documentation/arm64/silicon-errata.rst
@@ -106,6 +106,8 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A510 | #2077057 | ARM64_ERRATUM_2077057 |
+----------------+-----------------+-----------------+-----------------------------+
+| ARM | Cortex-A510 | #2441009 | ARM64_ERRATUM_2441009 |
++----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 |
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index a5d1b561ed53..001eaba5a6b4 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -838,6 +838,23 @@ config ARM64_ERRATUM_2224489
If unsure, say Y.
+config ARM64_ERRATUM_2441009
+ bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
+ default y
+ select ARM64_WORKAROUND_REPEAT_TLBI
+ help
+ This option adds a workaround for ARM Cortex-A510 erratum #2441009.
+
+ Under very rare circumstances, affected Cortex-A510 CPUs
+ may not handle a race between a break-before-make sequence on one
+ CPU, and another CPU accessing the same page. This could allow a
+ store to a page that has been unmapped.
+
+ Work around this by adding the affected CPUs to the list that needs
+ TLB sequences to be done twice.
+
+ If unsure, say Y.
+
config ARM64_ERRATUM_2064142
bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
depends on CORESIGHT_TRBE
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 6b92989f4cc2..aa9609e6ca67 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -211,6 +211,12 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
/* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */
ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe),
},
+#endif
+#ifdef CONFIG_ARM64_ERRATUM_2441009
+ {
+ /* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */
+ ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1),
+ },
#endif
{},
};
@@ -488,7 +494,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
#endif
#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
{
- .desc = "Qualcomm erratum 1009, or ARM erratum 1286807",
+ .desc = "Qualcomm erratum 1009, or ARM erratum 1286807, 2441009",
.capability = ARM64_WORKAROUND_REPEAT_TLBI,
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
.matches = cpucap_multi_entry_cap_matches,
--
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH] arm64: errata: Add Cortex-A510 to the repeat tlbi list
2022-08-30 15:08 [PATCH] arm64: errata: Add Cortex-A510 to the repeat tlbi list Lucas Wei
@ 2022-08-30 15:13 ` Lucas Wei
2022-08-30 15:22 ` Greg KH
2022-08-30 15:22 ` Greg KH
1 sibling, 1 reply; 6+ messages in thread
From: Lucas Wei @ 2022-08-30 15:13 UTC (permalink / raw)
To: stable, Greg KH
Cc: Robin Peng, Will Deacon, Aaron Ding, Daniel Mentz, James Morse
Hi Greg,
I send this mail through git send-email from kernel
guide(https://www.kernel.org/doc/html/v4.10/process/email-clients.html).
Would you help to confirm this could be applied on linux-5.15.y? Great thanks.
- Lucas
On Tue, Aug 30, 2022 at 11:08 PM Lucas Wei <lucaswei@google.com> wrote:
>
> From: James Morse <james.morse@arm.com>
>
> Cortex-A510 is affected by an erratum where in rare circumstances the
> CPUs may not handle a race between a break-before-make sequence on one
> CPU, and another CPU accessing the same page. This could allow a store
> to a page that has been unmapped.
>
> Work around this by adding the affected CPUs to the list that needs
> TLB sequences to be done twice.
>
> Signed-off-by: James Morse <james.morse@arm.com>
> Link: https://lore.kernel.org/r/20220704155732.21216-1-james.morse@arm.com
> Signed-off-by: Will Deacon <will@kernel.org>
> ---
> Documentation/arm64/silicon-errata.rst | 2 ++
> arch/arm64/Kconfig | 17 +++++++++++++++++
> arch/arm64/kernel/cpu_errata.c | 8 +++++++-
> 3 files changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
> index 0b4235b1f8c4..33b04db8408f 100644
> --- a/Documentation/arm64/silicon-errata.rst
> +++ b/Documentation/arm64/silicon-errata.rst
> @@ -106,6 +106,8 @@ stable kernels.
> +----------------+-----------------+-----------------+-----------------------------+
> | ARM | Cortex-A510 | #2077057 | ARM64_ERRATUM_2077057 |
> +----------------+-----------------+-----------------+-----------------------------+
> +| ARM | Cortex-A510 | #2441009 | ARM64_ERRATUM_2441009 |
> ++----------------+-----------------+-----------------+-----------------------------+
> | ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 |
> +----------------+-----------------+-----------------+-----------------------------+
> | ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 |
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index a5d1b561ed53..001eaba5a6b4 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -838,6 +838,23 @@ config ARM64_ERRATUM_2224489
>
> If unsure, say Y.
>
> +config ARM64_ERRATUM_2441009
> + bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
> + default y
> + select ARM64_WORKAROUND_REPEAT_TLBI
> + help
> + This option adds a workaround for ARM Cortex-A510 erratum #2441009.
> +
> + Under very rare circumstances, affected Cortex-A510 CPUs
> + may not handle a race between a break-before-make sequence on one
> + CPU, and another CPU accessing the same page. This could allow a
> + store to a page that has been unmapped.
> +
> + Work around this by adding the affected CPUs to the list that needs
> + TLB sequences to be done twice.
> +
> + If unsure, say Y.
> +
> config ARM64_ERRATUM_2064142
> bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
> depends on CORESIGHT_TRBE
> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index 6b92989f4cc2..aa9609e6ca67 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -211,6 +211,12 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
> /* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */
> ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe),
> },
> +#endif
> +#ifdef CONFIG_ARM64_ERRATUM_2441009
> + {
> + /* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */
> + ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1),
> + },
> #endif
> {},
> };
> @@ -488,7 +494,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
> #endif
> #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
> {
> - .desc = "Qualcomm erratum 1009, or ARM erratum 1286807",
> + .desc = "Qualcomm erratum 1009, or ARM erratum 1286807, 2441009",
> .capability = ARM64_WORKAROUND_REPEAT_TLBI,
> .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
> .matches = cpucap_multi_entry_cap_matches,
> --
>
>
--
Lucas Wei
Embedded Software Engineer
lucaswei@google.com
0287260408
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] arm64: errata: Add Cortex-A510 to the repeat tlbi list
2022-08-30 15:13 ` Lucas Wei
@ 2022-08-30 15:22 ` Greg KH
0 siblings, 0 replies; 6+ messages in thread
From: Greg KH @ 2022-08-30 15:22 UTC (permalink / raw)
To: Lucas Wei
Cc: stable, Robin Peng, Will Deacon, Aaron Ding, Daniel Mentz,
James Morse
A: http://en.wikipedia.org/wiki/Top_post
Q: Were do I find info about this thing called top-posting?
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing in e-mail?
A: No.
Q: Should I include quotations after my reply?
http://daringfireball.net/2007/07/on_top
On Tue, Aug 30, 2022 at 11:13:31PM +0800, Lucas Wei wrote:
> Hi Greg,
>
> I send this mail through git send-email from kernel
> guide(https://www.kernel.org/doc/html/v4.10/process/email-clients.html).
> Would you help to confirm this could be applied on linux-5.15.y? Great thanks.
See my other response, what git id is this in Linus's tree?
Always give us context on what to do please.
thanks,
greg k-h
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] arm64: errata: Add Cortex-A510 to the repeat tlbi list
2022-08-30 15:08 [PATCH] arm64: errata: Add Cortex-A510 to the repeat tlbi list Lucas Wei
2022-08-30 15:13 ` Lucas Wei
@ 2022-08-30 15:22 ` Greg KH
1 sibling, 0 replies; 6+ messages in thread
From: Greg KH @ 2022-08-30 15:22 UTC (permalink / raw)
To: Lucas Wei
Cc: stable, robinpeng, willdeacon, aaronding, danielmentz,
James Morse
On Tue, Aug 30, 2022 at 11:08:04PM +0800, Lucas Wei wrote:
> From: James Morse <james.morse@arm.com>
>
> Cortex-A510 is affected by an erratum where in rare circumstances the
> CPUs may not handle a race between a break-before-make sequence on one
> CPU, and another CPU accessing the same page. This could allow a store
> to a page that has been unmapped.
>
> Work around this by adding the affected CPUs to the list that needs
> TLB sequences to be done twice.
>
> Signed-off-by: James Morse <james.morse@arm.com>
> Link: https://lore.kernel.org/r/20220704155732.21216-1-james.morse@arm.com
> Signed-off-by: Will Deacon <will@kernel.org>
> ---
> Documentation/arm64/silicon-errata.rst | 2 ++
> arch/arm64/Kconfig | 17 +++++++++++++++++
> arch/arm64/kernel/cpu_errata.c | 8 +++++++-
> 3 files changed, 26 insertions(+), 1 deletion(-)
What is the upstream commit id of this patch in Linus's tree, and what
tree(s) do you want it applied to?
Always be specific, remember, some of us have to deal with over a
thousand emails a day...
thanks,
greg k-h
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] arm64: errata: Add Cortex-A510 to the repeat tlbi list
@ 2022-08-31 13:27 Lucas Wei
2022-09-01 9:56 ` Greg KH
0 siblings, 1 reply; 6+ messages in thread
From: Lucas Wei @ 2022-08-31 13:27 UTC (permalink / raw)
To: stable, gregkh
Cc: lucaswei, robinpeng, willdeacon, aaronding, danielmentz,
James Morse
From: James Morse <james.morse@arm.com>
commit 39fdb65f52e9a53d32a6ba719f96669fd300ae78 upstream.
Cortex-A510 is affected by an erratum where in rare circumstances the
CPUs may not handle a race between a break-before-make sequence on one
CPU, and another CPU accessing the same page. This could allow a store
to a page that has been unmapped.
Work around this by adding the affected CPUs to the list that needs
TLB sequences to be done twice.
Cc: stable@vger.kernel.org # 5.15.x
Signed-off-by: James Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20220704155732.21216-1-james.morse@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Lucas Wei <lucaswei@google.com>
---
Documentation/arm64/silicon-errata.rst | 2 ++
arch/arm64/Kconfig | 17 +++++++++++++++++
arch/arm64/kernel/cpu_errata.c | 8 +++++++-
3 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
index 7c1750bcc5bd..46644736e583 100644
--- a/Documentation/arm64/silicon-errata.rst
+++ b/Documentation/arm64/silicon-errata.rst
@@ -92,6 +92,8 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 |
+----------------+-----------------+-----------------+-----------------------------+
+| ARM | Cortex-A510 | #2441009 | ARM64_ERRATUM_2441009 |
++----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-N1 | #1349291 | N/A |
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 69e7e293f72e..9d80c783142f 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -666,6 +666,23 @@ config ARM64_ERRATUM_1508412
If unsure, say Y.
+config ARM64_ERRATUM_2441009
+ bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
+ default y
+ select ARM64_WORKAROUND_REPEAT_TLBI
+ help
+ This option adds a workaround for ARM Cortex-A510 erratum #2441009.
+
+ Under very rare circumstances, affected Cortex-A510 CPUs
+ may not handle a race between a break-before-make sequence on one
+ CPU, and another CPU accessing the same page. This could allow a
+ store to a page that has been unmapped.
+
+ Work around this by adding the affected CPUs to the list that needs
+ TLB sequences to be done twice.
+
+ If unsure, say Y.
+
config CAVIUM_ERRATUM_22375
bool "Cavium erratum 22375, 24313"
default y
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index c67c19d70159..e1be45fc7f5b 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -211,6 +211,12 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
/* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */
ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe),
},
+#endif
+#ifdef CONFIG_ARM64_ERRATUM_2441009
+ {
+ /* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */
+ ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1),
+ },
#endif
{},
};
@@ -427,7 +433,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
#endif
#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
{
- .desc = "Qualcomm erratum 1009, or ARM erratum 1286807",
+ .desc = "Qualcomm erratum 1009, or ARM erratum 1286807, 2441009",
.capability = ARM64_WORKAROUND_REPEAT_TLBI,
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
.matches = cpucap_multi_entry_cap_matches,
base-commit: addc9003c2e895fe8a068a66de1de6fdb4c6ac60
--
2.37.2.672.g94769d06f0-goog
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH] arm64: errata: Add Cortex-A510 to the repeat tlbi list
2022-08-31 13:27 Lucas Wei
@ 2022-09-01 9:56 ` Greg KH
0 siblings, 0 replies; 6+ messages in thread
From: Greg KH @ 2022-09-01 9:56 UTC (permalink / raw)
To: Lucas Wei
Cc: stable, robinpeng, willdeacon, aaronding, danielmentz,
James Morse
On Wed, Aug 31, 2022 at 09:27:25PM +0800, Lucas Wei wrote:
> From: James Morse <james.morse@arm.com>
>
> commit 39fdb65f52e9a53d32a6ba719f96669fd300ae78 upstream.
>
> Cortex-A510 is affected by an erratum where in rare circumstances the
> CPUs may not handle a race between a break-before-make sequence on one
> CPU, and another CPU accessing the same page. This could allow a store
> to a page that has been unmapped.
>
> Work around this by adding the affected CPUs to the list that needs
> TLB sequences to be done twice.
>
> Cc: stable@vger.kernel.org # 5.15.x
> Signed-off-by: James Morse <james.morse@arm.com>
> Link: https://lore.kernel.org/r/20220704155732.21216-1-james.morse@arm.com
> Signed-off-by: Will Deacon <will@kernel.org>
> Signed-off-by: Lucas Wei <lucaswei@google.com>
> ---
> Documentation/arm64/silicon-errata.rst | 2 ++
> arch/arm64/Kconfig | 17 +++++++++++++++++
> arch/arm64/kernel/cpu_errata.c | 8 +++++++-
> 3 files changed, 26 insertions(+), 1 deletion(-)
Now queued up, thanks.
greg k-h
^ permalink raw reply [flat|nested] 6+ messages in thread
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