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Date: Fri, 13 Dec 2024 15:38:56 +0100
From: Niklas Cassel <cassel@kernel.org>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: Jingoo Han <jingoohan1@gmail.com>,
	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
	Lorenzo Pieralisi <lpieralisi@kernel.org>,
	Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= <kw@linux.com>,
	Rob Herring <robh@kernel.org>, Bjorn Helgaas <bhelgaas@google.com>,
	Kishon Vijay Abraham I <kishon@kernel.org>,
	Damien Le Moal <dlemoal@kernel.org>, Frank Li <Frank.Li@nxp.com>,
	Jesper Nilsson <jesper.nilsson@axis.com>, stable@vger.kernel.org,
	linux-pci@vger.kernel.org
Subject: Re: [PATCH v5 1/6] PCI: dwc: ep: iATU registers must be written
 after the BAR_MASK
Message-ID: <Z1xHAOSiNssDBz3N@ryzen>
References: <20241127103016.3481128-9-cassel@kernel.org>
 <20241204173352.GA3006363@bhelgaas>
 <Z1w364da43KCOIGY@ryzen>
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In-Reply-To: <Z1w364da43KCOIGY@ryzen>

Hello Bjorn,

On Fri, Dec 13, 2024 at 02:34:35PM +0100, Niklas Cassel wrote:
> > 
> > And I guess the problem is that the previous code does:
> > 
> >   dw_pcie_ep_inbound_atu        # iATU
> >   dw_pcie_ep_writel_dbi2        # BAR_MASK (?)
> >   dw_pcie_ep_writel_dbi
> > 
> > and the new code basically does this:
> > 
> >   if (ep->epf_bar[bar]) {
> >     dw_pcie_ep_writel_dbi2      # BAR_MASK (?)
> >     dw_pcie_ep_writel_dbi
> >   }
> >   dw_pcie_ep_inbound_atu        # iATU
> >   ep->epf_bar[bar] = epf_bar
> > 
> > so the first time we call dw_pcie_ep_set_bar(), we write BAR_MASK
> > before iATU, and if we call dw_pcie_ep_set_bar() again, we skip the 
> > BAR_MASK update?
> 
> The problem is as described in the commit message:
> "If we do not write the BAR_MASK before writing the iATU registers, we are
> relying the reset value of the BAR_MASK being larger than the requested
> size of the first set_bar() call. The reset value of the BAR_MASK is SoC
> dependent."

Re-reading this commit message, I can see that it is a bit confusing.

I re-wrote the commit messages for patch 1/2 and patch 2/6 in this series,
based on your feedback. (I also updated the code comment in patch 2/6.)

I hope that it slightly clearer now :)

Please review:
https://lore.kernel.org/linux-pci/20241213143301.4158431-8-cassel@kernel.org/T/#u


Kind regards,
Niklas