Re: [PATCH v3] soc: qcom: llcc: Fix slice configuration values for SC8280XP

[Johan Hovold <johan@kernel.org>]

On Sun, Feb 19, 2023 at 06:57:01PM +0200, Abel Vesa wrote:
> The slice IDs for CVPFW, CPUSS1 and CPUWHT currently overflow the 32bit
> LLCC config registers. Fix that by using the slice ID values taken from
> the latest LLCC SC table.

This still doesn't really explain what the impact of this bug is (e.g.
for people doing backports), but I guess this will do.

> Fixes: ec69dfbdc426 ("soc: qcom: llcc: Add sc8180x and sc8280xp configurations")
> Cc: stable@vger.kernel.org	# 5.19+
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> Tested-by: Juerg Haefliger <juerg.haefliger@canonical.com>
> Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Reviewed-by: Johan Hovold <johan+linaro@kernel.org>

> ---
> 
> The v2 is here:
> https://lore.kernel.org/all/20230127144724.1292580-1-abel.vesa@linaro.org/
> 
> Changes since v2:
>  * specifically mentioned the 3 slice IDs that are being fixed and
>    what is happening without this patch
>  * added stabke Cc line
>  * added Juerg's T-b tag
>  * added Sai's R-b tag
>  * added Konrad's A-b tag
> 
> Changes since v1:
>  * dropped the LLCC_GPU and LLCC_WRCACHE max_cap changes
>  * took the new values from documentatio this time rather than
>    downstream kernel
> 
>  drivers/soc/qcom/llcc-qcom.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
> index 23ce2f78c4ed..26efe12012a0 100644
> --- a/drivers/soc/qcom/llcc-qcom.c
> +++ b/drivers/soc/qcom/llcc-qcom.c
> @@ -191,9 +191,9 @@ static const struct llcc_slice_config sc8280xp_data[] = {
>  	{ LLCC_CVP,      28, 512,  3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
>  	{ LLCC_APTCM,    30, 1024, 3, 1, 0x0,   0x1, 1, 0, 0, 1, 0, 0 },
>  	{ LLCC_WRCACHE,  31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
> -	{ LLCC_CVPFW,    32, 512,  1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
> -	{ LLCC_CPUSS1,   33, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
> -	{ LLCC_CPUHWT,   36, 512,  1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
> +	{ LLCC_CVPFW,    17, 512,  1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
> +	{ LLCC_CPUSS1,   3, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
> +	{ LLCC_CPUHWT,   5, 512,  1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
>  };
>  
>  static const struct llcc_slice_config sdm845_data[] =  {