* [PATCH v3] soc: qcom: llcc: Fix slice configuration values for SC8280XP
@ 2023-02-19 16:57 Abel Vesa
2023-03-06 13:01 ` Johan Hovold
2023-03-07 4:20 ` Bjorn Andersson
0 siblings, 2 replies; 5+ messages in thread
From: Abel Vesa @ 2023-02-19 16:57 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Johan Hovold,
Sai Prakash Ranjan, Juerg Haefliger
Cc: linux-arm-msm, Linux Kernel Mailing List, stable
The slice IDs for CVPFW, CPUSS1 and CPUWHT currently overflow the 32bit
LLCC config registers. Fix that by using the slice ID values taken from
the latest LLCC SC table.
Fixes: ec69dfbdc426 ("soc: qcom: llcc: Add sc8180x and sc8280xp configurations")
Cc: stable@vger.kernel.org # 5.19+
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Tested-by: Juerg Haefliger <juerg.haefliger@canonical.com>
Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
The v2 is here:
https://lore.kernel.org/all/20230127144724.1292580-1-abel.vesa@linaro.org/
Changes since v2:
* specifically mentioned the 3 slice IDs that are being fixed and
what is happening without this patch
* added stabke Cc line
* added Juerg's T-b tag
* added Sai's R-b tag
* added Konrad's A-b tag
Changes since v1:
* dropped the LLCC_GPU and LLCC_WRCACHE max_cap changes
* took the new values from documentatio this time rather than
downstream kernel
drivers/soc/qcom/llcc-qcom.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 23ce2f78c4ed..26efe12012a0 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -191,9 +191,9 @@ static const struct llcc_slice_config sc8280xp_data[] = {
{ LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
{ LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0, 0 },
{ LLCC_WRCACHE, 31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
- { LLCC_CVPFW, 32, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
- { LLCC_CPUSS1, 33, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
- { LLCC_CPUHWT, 36, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
+ { LLCC_CVPFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
+ { LLCC_CPUSS1, 3, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
+ { LLCC_CPUHWT, 5, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
};
static const struct llcc_slice_config sdm845_data[] = {
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH v3] soc: qcom: llcc: Fix slice configuration values for SC8280XP
2023-02-19 16:57 [PATCH v3] soc: qcom: llcc: Fix slice configuration values for SC8280XP Abel Vesa
@ 2023-03-06 13:01 ` Johan Hovold
2023-03-06 13:57 ` Abel Vesa
2023-03-07 4:20 ` Bjorn Andersson
1 sibling, 1 reply; 5+ messages in thread
From: Johan Hovold @ 2023-03-06 13:01 UTC (permalink / raw)
To: Abel Vesa
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Sai Prakash Ranjan,
Juerg Haefliger, linux-arm-msm, Linux Kernel Mailing List, stable
On Sun, Feb 19, 2023 at 06:57:01PM +0200, Abel Vesa wrote:
> The slice IDs for CVPFW, CPUSS1 and CPUWHT currently overflow the 32bit
> LLCC config registers. Fix that by using the slice ID values taken from
> the latest LLCC SC table.
This still doesn't really explain what the impact of this bug is (e.g.
for people doing backports), but I guess this will do.
> Fixes: ec69dfbdc426 ("soc: qcom: llcc: Add sc8180x and sc8280xp configurations")
> Cc: stable@vger.kernel.org # 5.19+
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> Tested-by: Juerg Haefliger <juerg.haefliger@canonical.com>
> Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
> ---
>
> The v2 is here:
> https://lore.kernel.org/all/20230127144724.1292580-1-abel.vesa@linaro.org/
>
> Changes since v2:
> * specifically mentioned the 3 slice IDs that are being fixed and
> what is happening without this patch
> * added stabke Cc line
> * added Juerg's T-b tag
> * added Sai's R-b tag
> * added Konrad's A-b tag
>
> Changes since v1:
> * dropped the LLCC_GPU and LLCC_WRCACHE max_cap changes
> * took the new values from documentatio this time rather than
> downstream kernel
>
> drivers/soc/qcom/llcc-qcom.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
> index 23ce2f78c4ed..26efe12012a0 100644
> --- a/drivers/soc/qcom/llcc-qcom.c
> +++ b/drivers/soc/qcom/llcc-qcom.c
> @@ -191,9 +191,9 @@ static const struct llcc_slice_config sc8280xp_data[] = {
> { LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
> { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0, 0 },
> { LLCC_WRCACHE, 31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
> - { LLCC_CVPFW, 32, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
> - { LLCC_CPUSS1, 33, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
> - { LLCC_CPUHWT, 36, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
> + { LLCC_CVPFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
> + { LLCC_CPUSS1, 3, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
> + { LLCC_CPUHWT, 5, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
> };
>
> static const struct llcc_slice_config sdm845_data[] = {
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH v3] soc: qcom: llcc: Fix slice configuration values for SC8280XP
2023-03-06 13:01 ` Johan Hovold
@ 2023-03-06 13:57 ` Abel Vesa
2023-03-06 14:16 ` Johan Hovold
0 siblings, 1 reply; 5+ messages in thread
From: Abel Vesa @ 2023-03-06 13:57 UTC (permalink / raw)
To: Johan Hovold
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Sai Prakash Ranjan,
Juerg Haefliger, linux-arm-msm, Linux Kernel Mailing List, stable
On 23-03-06 14:01:20, Johan Hovold wrote:
> On Sun, Feb 19, 2023 at 06:57:01PM +0200, Abel Vesa wrote:
> > The slice IDs for CVPFW, CPUSS1 and CPUWHT currently overflow the 32bit
> > LLCC config registers. Fix that by using the slice ID values taken from
> > the latest LLCC SC table.
>
> This still doesn't really explain what the impact of this bug is (e.g.
> for people doing backports), but I guess this will do.
>
Sent a v4 here:
https://lore.kernel.org/all/20230306135527.509796-1-abel.vesa@linaro.org/
> > Fixes: ec69dfbdc426 ("soc: qcom: llcc: Add sc8180x and sc8280xp configurations")
> > Cc: stable@vger.kernel.org # 5.19+
> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> > Tested-by: Juerg Haefliger <juerg.haefliger@canonical.com>
> > Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
> > Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>
> Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Added your R-b tag.
Thanks.
>
> > ---
> >
> > The v2 is here:
> > https://lore.kernel.org/all/20230127144724.1292580-1-abel.vesa@linaro.org/
> >
> > Changes since v2:
> > * specifically mentioned the 3 slice IDs that are being fixed and
> > what is happening without this patch
> > * added stabke Cc line
> > * added Juerg's T-b tag
> > * added Sai's R-b tag
> > * added Konrad's A-b tag
> >
> > Changes since v1:
> > * dropped the LLCC_GPU and LLCC_WRCACHE max_cap changes
> > * took the new values from documentatio this time rather than
> > downstream kernel
> >
> > drivers/soc/qcom/llcc-qcom.c | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
> > index 23ce2f78c4ed..26efe12012a0 100644
> > --- a/drivers/soc/qcom/llcc-qcom.c
> > +++ b/drivers/soc/qcom/llcc-qcom.c
> > @@ -191,9 +191,9 @@ static const struct llcc_slice_config sc8280xp_data[] = {
> > { LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
> > { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0, 0 },
> > { LLCC_WRCACHE, 31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
> > - { LLCC_CVPFW, 32, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
> > - { LLCC_CPUSS1, 33, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
> > - { LLCC_CPUHWT, 36, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
> > + { LLCC_CVPFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
> > + { LLCC_CPUSS1, 3, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
> > + { LLCC_CPUHWT, 5, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
> > };
> >
> > static const struct llcc_slice_config sdm845_data[] = {
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH v3] soc: qcom: llcc: Fix slice configuration values for SC8280XP
2023-03-06 13:57 ` Abel Vesa
@ 2023-03-06 14:16 ` Johan Hovold
0 siblings, 0 replies; 5+ messages in thread
From: Johan Hovold @ 2023-03-06 14:16 UTC (permalink / raw)
To: Abel Vesa
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Sai Prakash Ranjan,
Juerg Haefliger, linux-arm-msm, Linux Kernel Mailing List, stable
On Mon, Mar 06, 2023 at 03:57:52PM +0200, Abel Vesa wrote:
> On 23-03-06 14:01:20, Johan Hovold wrote:
> > On Sun, Feb 19, 2023 at 06:57:01PM +0200, Abel Vesa wrote:
> > > The slice IDs for CVPFW, CPUSS1 and CPUWHT currently overflow the 32bit
> > > LLCC config registers. Fix that by using the slice ID values taken from
> > > the latest LLCC SC table.
> >
> > This still doesn't really explain what the impact of this bug is (e.g.
> > for people doing backports), but I guess this will do.
> >
>
> Sent a v4 here:
> https://lore.kernel.org/all/20230306135527.509796-1-abel.vesa@linaro.org/
Looks good, thanks!
Johan
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v3] soc: qcom: llcc: Fix slice configuration values for SC8280XP
2023-02-19 16:57 [PATCH v3] soc: qcom: llcc: Fix slice configuration values for SC8280XP Abel Vesa
2023-03-06 13:01 ` Johan Hovold
@ 2023-03-07 4:20 ` Bjorn Andersson
1 sibling, 0 replies; 5+ messages in thread
From: Bjorn Andersson @ 2023-03-07 4:20 UTC (permalink / raw)
To: Konrad Dybcio, Abel Vesa, Sai Prakash Ranjan, Johan Hovold,
Juerg Haefliger, Andy Gross
Cc: stable, linux-arm-msm, Linux Kernel Mailing List
On Sun, 19 Feb 2023 18:57:01 +0200, Abel Vesa wrote:
> The slice IDs for CVPFW, CPUSS1 and CPUWHT currently overflow the 32bit
> LLCC config registers. Fix that by using the slice ID values taken from
> the latest LLCC SC table.
>
>
Applied, thanks!
[1/1] soc: qcom: llcc: Fix slice configuration values for SC8280XP
commit: 77bf4b3ed42e31d29b255fcd6530fb7a1e217e89
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-03-07 4:17 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-02-19 16:57 [PATCH v3] soc: qcom: llcc: Fix slice configuration values for SC8280XP Abel Vesa
2023-03-06 13:01 ` Johan Hovold
2023-03-06 13:57 ` Abel Vesa
2023-03-06 14:16 ` Johan Hovold
2023-03-07 4:20 ` Bjorn Andersson
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox