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Date:   Fri, 21 Jul 2023 14:09:13 +0200
From:   Andi Shyti <andi.shyti@linux.intel.com>
To:     "Krzysztofik, Janusz" <janusz.krzysztofik@intel.com>
Cc:     "Cavitt, Jonathan" <jonathan.cavitt@intel.com>,
        "Roper, Matthew D" <matthew.d.roper@intel.com>,
        Chris Wilson <chris@chris-wilson.co.uk>,
        Mika Kuoppala <mika.kuoppala@linux.intel.com>,
        "Das, Nirmoy" <nirmoy.das@intel.com>,
        "Hajda, Andrzej" <andrzej.hajda@intel.com>,
        Andi Shyti <andi.shyti@linux.intel.com>,
        intel-gfx <intel-gfx@lists.freedesktop.org>,
        linux-stable <stable@vger.kernel.org>,
        dri-evel <dri-devel@lists.freedesktop.org>
Subject: Re: [v7,5/9] drm/i915/gt: Enable the CCS_FLUSH bit in the pipe
 control
Message-ID: <ZLp1aa2lbM3abmBG@ashyti-mobl2.lan>
References: <20230720210737.761400-6-andi.shyti@linux.intel.com>
 <4155037.1IzOArtZ34@jkrzyszt-mobl2.ger.corp.intel.com>
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Hi Janusz,

> > Enable the CCS_FLUSH bit 13 in the control pipe for render and
> > compute engines in platforms starting from Meteor Lake (BSPEC
> > 43904 and 47112).
> > 
> > Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
> 
> I'm not sure why you think that your change fixes that commit.  Can you please 
> explain?

Hardware folks have provided a new sequence for performing the
quiescing of the engines... that's how it is :)

Thanks,
Andi