From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2437EB64DC for ; Fri, 21 Jul 2023 10:24:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230239AbjGUKX7 (ORCPT ); Fri, 21 Jul 2023 06:23:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232351AbjGUKXf (ORCPT ); Fri, 21 Jul 2023 06:23:35 -0400 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B5F4210B for ; Fri, 21 Jul 2023 03:23:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689935014; x=1721471014; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=roGcLwE29qARgCVUB/cKB+LGRXB3cs5flNEyabnZoJQ=; b=Yl0eOUYYwCtMW3R/lMY0MXpf5+uoUPyn2UanOel1Jc5G3fduFMIY/aFo qaGGo6u4OB1J92e1a29Smwd/5/IdnW1gynK6M61fLqkML/l/kyj252zxa dWKykUURs2UhwLrEUOcwOTQ/RUT4UXkLx1ZipgeHsdoCb5W5jmrxqjKkc 1VAn9HS5XTS67FICdj1KG6B+yEM0q4NF+X7gBdsYxMpSFCaCsx42wY9uW RlG/1czw/+Q07KCLioqr5d2eW0uoI1/o9trlFcwtu3G/3AkVCZ1MHyu9b 9FlQzBHUC46HzQVzeNZyIUHX4J8BO/rW/Cm58sIxs2FL4BlcB/69uOYXa Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10777"; a="367027387" X-IronPort-AV: E=Sophos;i="6.01,220,1684825200"; d="scan'208";a="367027387" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2023 03:23:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10777"; a="702001407" X-IronPort-AV: E=Sophos;i="6.01,220,1684825200"; d="scan'208";a="702001407" Received: from hbockhor-mobl.ger.corp.intel.com (HELO intel.com) ([10.252.54.104]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2023 03:23:05 -0700 Date: Fri, 21 Jul 2023 12:23:02 +0200 From: Andi Shyti To: Andrzej Hajda Cc: Andi Shyti , Jonathan Cavitt , Matt Roper , Chris Wilson , Mika Kuoppala , Nirmoy Das , intel-gfx , linux-stable , dri-evel Subject: Re: [Intel-gfx] [PATCH v7 5/9] drm/i915/gt: Enable the CCS_FLUSH bit in the pipe control Message-ID: References: <20230720210737.761400-1-andi.shyti@linux.intel.com> <20230720210737.761400-6-andi.shyti@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org Hi Andrzej, > > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > > index 7566c89d9def3..9d050b9a19194 100644 > > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > > @@ -218,6 +218,13 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) > > bit_group_0 |= PIPE_CONTROL0_HDC_PIPELINE_FLUSH; > > + /* > > + * When required, in MTL+ platforms we need to > > + * set the CCS_FLUSH bit in the pipe control > > + */ > > + if (GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70)) > > + bit_group_0 |= PIPE_CONTROL_CCS_FLUSH; > > + > > > Btw, not for this patch, but related: rcs and ccs have slightly different > set of flushes according to bspec but this functions is the same for both. > Is it sth we should address, or just safe simplification. I guess this is not only used for ccs aux invalidation. I think the BSPEC is specifying the minimum set of bits that need to be set in the pipe control. So that I left it as it is and just added this bit for MTL+. Thanks, Andi