From: Andi Shyti <andi.shyti@linux.intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: Andi Shyti <andi.shyti@linux.intel.com>,
intel-gfx <intel-gfx@lists.freedesktop.org>,
dri-devel <dri-devel@lists.freedesktop.org>,
Chris Wilson <chris.p.wilson@linux.intel.com>,
Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
John Harrison <John.C.Harrison@intel.com>,
stable@vger.kernel.org, Andi Shyti <andi.shyti@kernel.org>,
Tvrtko Ursulin <tursulin@ursulin.net>
Subject: Re: [PATCH v5 1/4] drm/i915/gt: Disable HW load balancing for CCS
Date: Tue, 12 Mar 2024 21:37:50 +0100 [thread overview]
Message-ID: <ZfC9Ho6zAxjZDQ-O@ashyti-mobl2.lan> (raw)
In-Reply-To: <20240312165825.GK718896@mdroper-desk1.amr.corp.intel.com>
Hi Matt,
...
> > #define GEN12_RCU_MODE _MMIO(0x14800)
> > #define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0)
> > +#define XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1)
>
> Nitpick: we usually order register bits in descending order. Aside from
> that,
I can take care of it.
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Thanks!
Andi
next prev parent reply other threads:[~2024-03-12 20:38 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-08 20:22 [PATCH v5 0/4] Disable automatic load CCS load balancing Andi Shyti
2024-03-08 20:22 ` [PATCH v5 1/4] drm/i915/gt: Disable HW load balancing for CCS Andi Shyti
2024-03-12 16:58 ` Matt Roper
2024-03-12 20:37 ` Andi Shyti [this message]
2024-03-08 20:22 ` [PATCH v5 2/4] drm/i915/gt: Refactor uabi engine class/instance list creation Andi Shyti
2024-03-12 17:08 ` Matt Roper
2024-03-12 20:49 ` Andi Shyti
2024-03-08 20:22 ` [PATCH v5 3/4] drm/i915/gt: Disable tests for CCS engines beyond the first Andi Shyti
2024-03-08 20:25 ` kernel test robot
2024-03-08 20:22 ` [PATCH v5 4/4] drm/i915/gt: Enable only one CCS for compute workload Andi Shyti
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