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From: Niklas Cassel <cassel@kernel.org>
To: Richard Zhu <hongxing.zhu@nxp.com>
Cc: tj@kernel.org, dlemoal@kernel.org, robh@kernel.org,
	krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org,
	s.hauer@pengutronix.de, festevam@gmail.com,
	linux-ide@vger.kernel.org, stable@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev,
	kernel@pengutronix.de
Subject: Re: [PATCH v4 4/6] ata: ahci_imx: Add 32bits DMA limit for i.MX8QM AHCI SATA
Date: Tue, 23 Jul 2024 18:04:23 +0200	[thread overview]
Message-ID: <Zp/Uh/mavwo+755Q@x1-carbon.lan> (raw)
In-Reply-To: <1721367736-30156-5-git-send-email-hongxing.zhu@nxp.com>

On Fri, Jul 19, 2024 at 01:42:14PM +0800, Richard Zhu wrote:
> Since i.MX8QM AHCI SATA only has 32bits DMA capability.
> Add 32bits DMA limit here.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---
>  drivers/ata/ahci_imx.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c
> index 4dd98368f8562..e94c0fdea2260 100644
> --- a/drivers/ata/ahci_imx.c
> +++ b/drivers/ata/ahci_imx.c
> @@ -827,6 +827,9 @@ static const struct scsi_host_template ahci_platform_sht = {
>  
>  static int imx8_sata_probe(struct device *dev, struct imx_ahci_priv *imxpriv)
>  {
> +	if (!(dev->bus_dma_limit))
> +		dev->bus_dma_limit = DMA_BIT_MASK(32);
> +
>  	imxpriv->sata_phy = devm_phy_get(dev, "sata-phy");
>  	if (IS_ERR(imxpriv->sata_phy))
>  		return dev_err_probe(dev, PTR_ERR(imxpriv->sata_phy),
> -- 
> 2.37.1
> 

Why is this needed?

ahci_imx.c calls ahci_platform_init_host(), which calls
dma_coerce_mask_and_coherent():
https://github.com/torvalds/linux/blob/v6.10/drivers/ata/libahci_platform.c#L750-L756

Should this code perhaps look more like:
https://github.com/torvalds/linux/blob/v6.10/drivers/ata/ahci.c#L1048-L1054

where we set it to 64 or 32 bit explicitly.

Does this solve your problem:
diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c
index 581704e61f28..fc86e2c8c42b 100644
--- a/drivers/ata/libahci_platform.c
+++ b/drivers/ata/libahci_platform.c
@@ -747,12 +747,11 @@ int ahci_platform_init_host(struct platform_device *pdev,
                        ap->ops = &ata_dummy_port_ops;
        }
 
-       if (hpriv->cap & HOST_CAP_64) {
-               rc = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(64));
-               if (rc) {
-                       dev_err(dev, "Failed to enable 64-bit DMA.\n");
-                       return rc;
-               }
+       rc = dma_coerce_mask_and_coherent(dev,
+                       DMA_BIT_MASK((hpriv->cap & HOST_CAP_64) ? 64 : 32));
+       if (rc) {
+               dev_err(dev, "DMA enable failed\n");
+               return rc;
        }
 
        rc = ahci_reset_controller(host);



Kind regards,
Niklas

  parent reply	other threads:[~2024-07-23 16:04 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-19  5:42 [PATCH v4 0/6] Refine i.MX8QM SATA based on generic PHY callbacks Richard Zhu
2024-07-19  5:42 ` [PATCH v4 1/6] dt-bindings: ata: Add i.MX8QM AHCI compatible string Richard Zhu
2024-07-19  5:42 ` [PATCH v4 2/6] ata: ahci_imx: Clean up code by using i.MX8Q HSIO PHY driver Richard Zhu
2024-07-19  5:42 ` [PATCH v4 3/6] ata: ahci_imx: AHB clock rate setting is not required on i.MX8QM AHCI SATA Richard Zhu
2024-07-19  5:42 ` [PATCH v4 4/6] ata: ahci_imx: Add 32bits DMA limit for " Richard Zhu
2024-07-19  6:08   ` kernel test robot
2024-07-23 16:04   ` Niklas Cassel [this message]
2024-08-02  2:30     ` Hongxing Zhu
2024-08-07 22:35       ` Niklas Cassel
2024-08-08  6:21         ` Hongxing Zhu
2024-08-08 14:03         ` Frank Li
2024-08-08 16:24           ` Niklas Cassel
2024-08-09  8:45             ` Hongxing Zhu
2024-08-09 13:47               ` Niklas Cassel
2024-08-12  1:43                 ` Hongxing Zhu
2024-07-19  5:42 ` [PATCH v4 5/6] ata: ahci_imx: Enlarge RX water mark for i.MX8QM SATA Richard Zhu
2024-07-19  5:42 ` [PATCH v4 6/6] ata: ahci_imx: Correct the email address Richard Zhu

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