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Wed, 25 Mar 2026 17:59:49 +0000 (GMT) Message-ID: Date: Wed, 25 Mar 2026 23:29:48 +0530 Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RESEND RFC PATCH v3 1/6] drm/amdgpu: Change AMDGPU_VA_RESERVED_TRAP_SIZE to 2 PAGE_SIZE pages To: "Kuehling, Felix" , =?UTF-8?Q?Christian_K=C3=B6nig?= , amd-gfx@lists.freedesktop.org, Alex Deucher , Alex Deucher , Philip Yang Cc: David.YatSin@amd.com, Kent.Russell@amd.com, Ritesh Harjani , Vaidyanathan Srinivasan , stable@vger.kernel.org References: <65a96159-1266-4b42-91ce-359fcd1a76ea@amd.com> <7beedf3b-99f7-4096-9a49-88f98b9b4eb5@linux.ibm.com> <6171f849-4164-4fd5-b31e-79c08df936c2@linux.ibm.com> <6b2d502d-08ef-4008-8399-f5630de2385c@amd.com> <79783c4d-13cb-4ae9-b2ba-45c066fb515a@linux.ibm.com> <00db9c57-9d16-4123-8e2c-b9251aa702ad@amd.com> Content-Language: en-US From: Donet Tom In-Reply-To: <00db9c57-9d16-4123-8e2c-b9251aa702ad@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzI1MDEyOSBTYWx0ZWRfX50dG+MjqkT1A BsVodQipM9y5640MP8Ec/Y7aUeQd20rZERkwfPz0XrcdvULDlUvX8rgc/3NhH80R1EMw1UkNFHy Zpbe7aSeYVXV0S+r3s1+GeKAszqwttJHxVCct9xIFo8YDnTtADw1SMvUwBHyps1cGngCt7jmw8u h/rOIrZRwuvpMeqBRl4UTcK+Cf6u3XB4JgUJKi3faz1l145A4AKYnxMEVgVIXIpt/wI/fIbmYIV Rnem28kq/3C0Xl+JcryYWcaL3rBAhu4UlfhKLc9bQ3rg7SN8np9qjE/Wdre/wzEk+CTl9S5Pk12 69u3zE9fFkDv6HshPvU5fz61YkvOUtCq9fV+oeyljhEvhM2oQWrMjdqh3qzfIylSFkANo/iAGvz RptvyZfjPqQwtV07wRjrB4TsqKyf7STD7Dusw6EQmmkb0eg0o3udwwFBae3tvqvCbSq00yPsPbR V6bZ/dxEjwv4XH6FMVA== X-Authority-Analysis: v=2.4 cv=JK42csKb c=1 sm=1 tr=0 ts=69c4229b cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=V8glGbnc2Ofi9Qvn3v5h:22 a=ollYYA0SzF1M6iY1_W8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-ORIG-GUID: ekjZwXEy9GgvTq3WbrXk0jI6skmz2Kuq X-Proofpoint-GUID: kM32Gd8ZLGdEom41q2w1sYfJ--8yTsty X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-25_05,2026-03-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 adultscore=0 spamscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603250129 On 3/25/26 11:24 PM, Kuehling, Felix wrote: > > On 2026-03-25 06:29, Christian König wrote: >>> Hi @Christian @Felix >>> >>> Thanks for the review. >>> >>> I have made the suggested change. I am now reserving 64 KB >>> in the  address space for the trap, while allocating >>> only 8 KB for both 4K and 64K page sizes. With this change, >>> I am no longer seeing crashes on either 4K or 64K systems. >>> >>> Does this approach look reasonable to you? >> Looks correct to me, but Felix clearly has the last word on that. > > That works for me as well. Thank you , Felix. I will incorporate this change and post an updated version. -Donet > > Thanks, >   Felix > > >> >> Regards, >> Christian. >> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h >>> index bb276c0ad06d..d5b7061556ba 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h >>> @@ -173,7 +173,7 @@ struct amdgpu_bo_vm; >>>   #define AMDGPU_VA_RESERVED_SEQ64_SIZE          (2ULL << 20) >>>   #define AMDGPU_VA_RESERVED_SEQ64_START(adev) >>>  (AMDGPU_VA_RESERVED_CSA_START(adev) \ >>>                                                   - >>> AMDGPU_VA_RESERVED_SEQ64_SIZE) >>> -#define AMDGPU_VA_RESERVED_TRAP_SIZE           (2ULL << 12) >>> +#define AMDGPU_VA_RESERVED_TRAP_SIZE           (1ULL << 16) >>>   #define AMDGPU_VA_RESERVED_TRAP_START(adev) >>> (AMDGPU_VA_RESERVED_SEQ64_START(adev) \ >>>                                                   - >>> AMDGPU_VA_RESERVED_TRAP_SIZE) >>>   #define AMDGPU_VA_RESERVED_BOTTOM              (1ULL << 16) >>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h >>> b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h >>> index e5b56412931b..035687a17d89 100644 >>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h >>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h >>> @@ -102,8 +102,8 @@ >>>    * The first chunk is the TBA used for the CWSR ISA code. The second >>>    * chunk is used as TMA for user-mode trap handler setup in >>> daisy-chain mode. >>>    */ >>> -#define KFD_CWSR_TBA_TMA_SIZE (PAGE_SIZE * 2) >>> -#define KFD_CWSR_TMA_OFFSET (PAGE_SIZE + 2048) >>> +#define KFD_CWSR_TBA_TMA_SIZE (AMDGPU_GPU_PAGE_SIZE * 2) >>> +#define KFD_CWSR_TMA_OFFSET (AMDGPU_GPU_PAGE_SIZE + 2048) >>> >>>   #define KFD_MAX_NUM_OF_QUEUES_PER_DEVICE               \ >>>          (KFD_MAX_NUM_OF_PROCESSES *