Re: [PATCH v2] iommu/amd: Fix geometry.aperture_end for V2 tables

[Will Deacon <will@kernel.org>]

Hi Jason, Vasant,

On Wed, Jul 16, 2025 at 09:49:29AM -0300, Jason Gunthorpe wrote:
> On Thu, Jun 12, 2025 at 10:54:00AM +0530, Vasant Hegde wrote:
> > > Adjust dma_max_address() to remove the top VA bit. It now returns:
> > > 
> > > 5 Level:
> > >   Before 0x1ffffffffffffff
> > >   After  0x0ffffffffffffff
> > > 4 Level:
> > >   Before 0xffffffffffff
> > >   After  0x7fffffffffff
> > > 
> > > Fixes: 11c439a19466 ("iommu/amd/pgtbl_v2: Fix domain max address")
> > > Link: https://lore.kernel.org/all/8858d4d6-d360-4ef0-935c-bfd13ea54f42@amd.com/
> > > Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
> > 
> > Reviewed-by: Vasant Hegde <vasant.hegde@amd.com>
> 
> Will, can you pick this up please? It seems to have been overlooked

Thanks, I had missed this one (I only trawled the list for the two weeks
prior to Joerg going on holiday).

I'll pick it up, but please now that the preceding:

	if (pgtable == PD_MODE_V1)

part now returns:

	PM_LEVEL_SIZE(amd_iommu_hpt_level);

instead of:

	~0ULL;

thanks to 025d1371cc8c ("iommu/amd: Add efr[HATS] max v1 page table
level"). I'm assuming that's fine because this change is about v2, but I
just wanted to highlight it in case there's a potential issue.

Will