From: Sean Christopherson <seanjc@google.com>
To: Sasha Levin <sashal@kernel.org>
Cc: stable@vger.kernel.org, Maxim Levitsky <mlevitsk@redhat.com>
Subject: Re: [PATCH 6.12.y 4/5] KVM: x86: model canonical checks more precisely
Date: Thu, 24 Jul 2025 08:38:43 -0700 [thread overview]
Message-ID: <aIJTg3JWW3LHBfuC@google.com> (raw)
In-Reply-To: <20250723151416.1092631-4-sashal@kernel.org>
On Wed, Jul 23, 2025, Sasha Levin wrote:
> From: Maxim Levitsky <mlevitsk@redhat.com>
>
> [ Upstream commit 9245fd6b8531497d129a7a6e3eef258042862f85 ]
>
> As a result of a recent investigation, it was determined that x86 CPUs
> which support 5-level paging, don't always respect CR4.LA57 when doing
> canonical checks.
>
> In particular:
>
> 1. MSRs which contain a linear address, allow full 57-bitcanonical address
> regardless of CR4.LA57 state. For example: MSR_KERNEL_GS_BASE.
>
> 2. All hidden segment bases and GDT/IDT bases also behave like MSRs.
> This means that full 57-bit canonical address can be loaded to them
> regardless of CR4.LA57, both using MSRS (e.g GS_BASE) and instructions
> (e.g LGDT).
>
> 3. TLB invalidation instructions also allow the user to use full 57-bit
> address regardless of the CR4.LA57.
>
> Finally, it must be noted that the CPU doesn't prevent the user from
> disabling 5-level paging, even when the full 57-bit canonical address is
> present in one of the registers mentioned above (e.g GDT base).
>
> In fact, this can happen without any userspace help, when the CPU enters
> SMM mode - some MSRs, for example MSR_KERNEL_GS_BASE are left to contain
> a non-canonical address in regard to the new mode.
>
> Since most of the affected MSRs and all segment bases can be read and
> written freely by the guest without any KVM intervention, this patch makes
> the emulator closely follow hardware behavior, which means that the
> emulator doesn't take in the account the guest CPUID support for 5-level
> paging, and only takes in the account the host CPU support.
>
> Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com>
> Link: https://lore.kernel.org/r/20240906221824.491834-4-mlevitsk@redhat.com
> Signed-off-by: Sean Christopherson <seanjc@google.com>
> Stable-dep-of: fa787ac07b3c ("KVM: x86/hyper-v: Skip non-canonical addresses during PV TLB flush")
> Signed-off-by: Sasha Levin <sashal@kernel.org>
> ---
Acked-by: Sean Christopherson <seanjc@google.com>
next prev parent reply other threads:[~2025-07-24 15:38 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-12 14:25 FAILED: patch "[PATCH] KVM: x86/hyper-v: Skip non-canonical addresses during PV TLB" failed to apply to 6.12-stable tree gregkh
2025-07-23 15:14 ` [PATCH 6.12.y 1/5] KVM: x86: drop x86.h include from cpuid.h Sasha Levin
2025-07-23 15:14 ` [PATCH 6.12.y 2/5] KVM: x86: Route non-canonical checks in emulator through emulate_ops Sasha Levin
2025-07-24 15:38 ` Sean Christopherson
2025-07-23 15:14 ` [PATCH 6.12.y 3/5] KVM: x86: Add X86EMUL_F_MSR and X86EMUL_F_DT_LOAD to aid canonical checks Sasha Levin
2025-07-24 15:38 ` Sean Christopherson
2025-07-23 15:14 ` [PATCH 6.12.y 4/5] KVM: x86: model canonical checks more precisely Sasha Levin
2025-07-24 15:38 ` Sean Christopherson [this message]
2025-07-23 15:14 ` [PATCH 6.12.y 5/5] KVM: x86/hyper-v: Skip non-canonical addresses during PV TLB flush Sasha Levin
2025-07-24 15:38 ` Sean Christopherson
2025-07-24 15:37 ` [PATCH 6.12.y 1/5] KVM: x86: drop x86.h include from cpuid.h Sean Christopherson
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