[PATCH v2 1/3] PCI: tegra194: Fix broken tegra_pcie_ep_raise_msi_irq()

[PATCH v2 1/3] PCI: tegra194: Fix broken tegra_pcie_ep_raise_msi_irq()

[Niklas Cassel]

The pci_epc_raise_irq() supplies a MSI or MSI-X interrupt number in range
(1-N), see kdoc for pci_epc_raise_irq().

Thus, for MSI pci_epc_raise_irq() will supply interrupt number 1-32.

Convert the interrupt number to an MSI vector.

With this, the PCI endpoint kselftest test case MSI_TEST passes.

Also, set msi_capable to true, as the driver obviously supports MSI.
This helps pci_endpoint_test to use the optimal IRQ type when using
PCITEST_IRQ_TYPE_AUTO.

Cc: stable@vger.kernel.org
Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
Signed-off-by: Niklas Cassel <cassel@kernel.org>
---
 drivers/pci/controller/dwc/pcie-tegra194.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 7c295ec6f0f16..63d310e5335f4 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1969,10 +1969,10 @@ static int tegra_pcie_ep_raise_intx_irq(struct tegra_pcie_dw *pcie, u16 irq)
 
 static int tegra_pcie_ep_raise_msi_irq(struct tegra_pcie_dw *pcie, u16 irq)
 {
-	if (unlikely(irq > 31))
+	if (unlikely(irq > 32))
 		return -EINVAL;
 
-	appl_writel(pcie, BIT(irq), APPL_MSI_CTRL_1);
+	appl_writel(pcie, BIT(irq - 1), APPL_MSI_CTRL_1);
 
 	return 0;
 }
@@ -2012,6 +2012,7 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
 
 static const struct pci_epc_features tegra_pcie_epc_features = {
 	.linkup_notifier = true,
+	.msi_capable = true,
 	.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M,
 			.only_64bit = true, },
 	.bar[BAR_1] = { .type = BAR_RESERVED, },
-- 
2.51.0

Re: [PATCH v2 1/3] PCI: tegra194: Fix broken tegra_pcie_ep_raise_msi_irq()

[Manivannan Sadhasivam]

On Mon, Sep 22, 2025 at 04:08:24PM +0200, Niklas Cassel wrote:
> The pci_epc_raise_irq() supplies a MSI or MSI-X interrupt number in range
> (1-N), see kdoc for pci_epc_raise_irq().
> 
> Thus, for MSI pci_epc_raise_irq() will supply interrupt number 1-32.
> 
> Convert the interrupt number to an MSI vector.
> 
> With this, the PCI endpoint kselftest test case MSI_TEST passes.
> 
> Also, set msi_capable to true, as the driver obviously supports MSI.
> This helps pci_endpoint_test to use the optimal IRQ type when using
> PCITEST_IRQ_TYPE_AUTO.
> 
> Cc: stable@vger.kernel.org
> Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
> Signed-off-by: Niklas Cassel <cassel@kernel.org>
> ---
>  drivers/pci/controller/dwc/pcie-tegra194.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 7c295ec6f0f16..63d310e5335f4 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -1969,10 +1969,10 @@ static int tegra_pcie_ep_raise_intx_irq(struct tegra_pcie_dw *pcie, u16 irq)
>  
>  static int tegra_pcie_ep_raise_msi_irq(struct tegra_pcie_dw *pcie, u16 irq)
>  {
> -	if (unlikely(irq > 31))
> +	if (unlikely(irq > 32))
>  		return -EINVAL;
>  
> -	appl_writel(pcie, BIT(irq), APPL_MSI_CTRL_1);
> +	appl_writel(pcie, BIT(irq - 1), APPL_MSI_CTRL_1);
>  
>  	return 0;
>  }
> @@ -2012,6 +2012,7 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>  
>  static const struct pci_epc_features tegra_pcie_epc_features = {
>  	.linkup_notifier = true,
> +	.msi_capable = true,

This change is unrelated to the above tegra_pcie_ep_raise_msi_irq() fix. So this
change should be in a separate patch.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v2 1/3] PCI: tegra194: Fix broken tegra_pcie_ep_raise_msi_irq()

[Manivannan Sadhasivam]

On Wed, Sep 24, 2025 at 09:24:09PM +0530, Manivannan Sadhasivam wrote:
> On Mon, Sep 22, 2025 at 04:08:24PM +0200, Niklas Cassel wrote:
> > The pci_epc_raise_irq() supplies a MSI or MSI-X interrupt number in range
> > (1-N), see kdoc for pci_epc_raise_irq().
> > 
> > Thus, for MSI pci_epc_raise_irq() will supply interrupt number 1-32.
> > 
> > Convert the interrupt number to an MSI vector.
> > 
> > With this, the PCI endpoint kselftest test case MSI_TEST passes.
> > 
> > Also, set msi_capable to true, as the driver obviously supports MSI.
> > This helps pci_endpoint_test to use the optimal IRQ type when using
> > PCITEST_IRQ_TYPE_AUTO.
> > 
> > Cc: stable@vger.kernel.org
> > Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
> > Signed-off-by: Niklas Cassel <cassel@kernel.org>
> > ---
> >  drivers/pci/controller/dwc/pcie-tegra194.c | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> > index 7c295ec6f0f16..63d310e5335f4 100644
> > --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> > +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> > @@ -1969,10 +1969,10 @@ static int tegra_pcie_ep_raise_intx_irq(struct tegra_pcie_dw *pcie, u16 irq)
> >  
> >  static int tegra_pcie_ep_raise_msi_irq(struct tegra_pcie_dw *pcie, u16 irq)
> >  {
> > -	if (unlikely(irq > 31))
> > +	if (unlikely(irq > 32))
> >  		return -EINVAL;
> >  
> > -	appl_writel(pcie, BIT(irq), APPL_MSI_CTRL_1);
> > +	appl_writel(pcie, BIT(irq - 1), APPL_MSI_CTRL_1);
> >  
> >  	return 0;
> >  }
> > @@ -2012,6 +2012,7 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> >  
> >  static const struct pci_epc_features tegra_pcie_epc_features = {
> >  	.linkup_notifier = true,
> > +	.msi_capable = true,
> 
> This change is unrelated to the above tegra_pcie_ep_raise_msi_irq() fix. So this
> change should be in a separate patch.
> 

I did the split and applied the series, thanks!

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v2 1/3] PCI: tegra194: Fix broken tegra_pcie_ep_raise_msi_irq()

[Niklas Cassel]

On Wed, Sep 24, 2025 at 09:58:20PM +0530, Manivannan Sadhasivam wrote:
> > > @@ -2012,6 +2012,7 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > >  
> > >  static const struct pci_epc_features tegra_pcie_epc_features = {
> > >  	.linkup_notifier = true,
> > > +	.msi_capable = true,
> > 
> > This change is unrelated to the above tegra_pcie_ep_raise_msi_irq() fix. So this
> > change should be in a separate patch.
> > 
> 
> I did the split and applied the series, thanks!

Thank you Mani!


Kind regards,
Niklas

[PATCH v2 2/3] PCI: tegra194: Reset BARs when running in PCIe endpoint mode

[Niklas Cassel]

Tegra already defines all BARs expect for BAR0 as BAR_RESERVED.
This is sufficient for pci-epf-test to not allocate backing memory and to
not call set_bar() for those BARs. However, marking a BAR as BAR_RESERVED
does not mean that the BAR get disabled.

The host side driver, pci_endpoint_test, simply does an ioremap for all
enabled BARs, and will run tests against all enabled BARs. (I.e. it will
run tests also against the BARs marked as BAR_RESERVED.)

After running the BARs tests (which will write to all enabled BARs), the
inbound address translation is broken.
This is because the tegra controller exposes the ATU Port Logic Structure
in BAR4. So when BAR4 is written, the inbound address translation settings
get overwritten.

To avoid this, implement the dw_pcie_ep_ops .init() callback and start off
by disabling all BARs (pci-epf-test will later enable/configure BARs that
are not defined as BAR_RESERVED).

This matches the behavior of other PCIe endpoint drivers:
dra7xx, imx6, layerscape-ep, artpec6, dw-rockchip, qcom-ep, rcar-gen4, and
uniphier-ep.

With this, the PCI endpoint kselftest test case CONSECUTIVE_BAR_TEST
(which was specifically made to detect address translation issues) passes.

Cc: stable@vger.kernel.org
Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
Signed-off-by: Niklas Cassel <cassel@kernel.org>
---
 drivers/pci/controller/dwc/pcie-tegra194.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 63d310e5335f4..7eb48cc13648e 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1955,6 +1955,15 @@ static irqreturn_t tegra_pcie_ep_pex_rst_irq(int irq, void *arg)
 	return IRQ_HANDLED;
 }
 
+static void tegra_pcie_ep_init(struct dw_pcie_ep *ep)
+{
+	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+	enum pci_barno bar;
+
+	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
+		dw_pcie_ep_reset_bar(pci, bar);
+};
+
 static int tegra_pcie_ep_raise_intx_irq(struct tegra_pcie_dw *pcie, u16 irq)
 {
 	/* Tegra194 supports only INTA */
@@ -2030,6 +2039,7 @@ tegra_pcie_ep_get_features(struct dw_pcie_ep *ep)
 }
 
 static const struct dw_pcie_ep_ops pcie_ep_ops = {
+	.init = tegra_pcie_ep_init,
 	.raise_irq = tegra_pcie_ep_raise_irq,
 	.get_features = tegra_pcie_ep_get_features,
 };
-- 
2.51.0

[PATCH v2 3/3] PCI: tegra194: Handle errors in BPMP response

[Niklas Cassel]

From: Vidya Sagar <vidyas@nvidia.com>

The return value from tegra_bpmp_transfer() indicates the success or
failure of the IPC transaction with BPMP. If the transaction
succeeded, we also need to check the actual command's result code.

If we don't have error handling for tegra_bpmp_transfer(), we will
set the pcie->ep_state to EP_STATE_ENABLED (even though the
tegra_bpmp_transfer() command failed). Thus, the pcie->ep_state will
get out of sync with reality, and any further PERST# assert + deassert
will be a no-op (will not trigger the hardware initialization sequence).

This is because pex_ep_event_pex_rst_deassert() checks the current
pcie->ep_state, and does nothing if the current state is already
EP_STATE_ENABLED.

Thus, it is important to have error handling for tegra_bpmp_transfer(),
such that the pcie->ep_state can not get out of sync with reality, so
that we will try to initialize the hardware not only during the first
PERST# assert + deassert, but also during any succeeding PERST# assert +
deassert.

One example where this fix is needed is when using a rock5b as host.
During the initial PERST# assert + deassert (triggered by the bootloader
on the rock5b) pex_ep_event_pex_rst_deassert() will get called, but for
some unknown reason, the tegra_bpmp_transfer() call to initialize the PHY
fails. Once Linux has been loaded on the rock5b, the PCIe driver will once
again assert + deassert PERST#. However, without tegra_bpmp_transfer()
error handling, this second PERST# assert + deassert will not trigger the
hardware initialization sequence.

With tegra_bpmp_transfer() error handling, the second PERST# assert +
deassert will once again trigger the hardware to be initialized and this
time the tegra_bpmp_transfer() succeeds.

Cc: stable@vger.kernel.org
Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
[cassel: improve commit log]
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Niklas Cassel <cassel@kernel.org>
---
 drivers/pci/controller/dwc/pcie-tegra194.c | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 7eb48cc13648e..c4265b3f72048 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1223,6 +1223,7 @@ static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie,
 	struct mrq_uphy_response resp;
 	struct tegra_bpmp_message msg;
 	struct mrq_uphy_request req;
+	int err;
 
 	/*
 	 * Controller-5 doesn't need to have its state set by BPMP-FW in
@@ -1245,7 +1246,13 @@ static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie,
 	msg.rx.data = &resp;
 	msg.rx.size = sizeof(resp);
 
-	return tegra_bpmp_transfer(pcie->bpmp, &msg);
+	err = tegra_bpmp_transfer(pcie->bpmp, &msg);
+	if (err)
+		return err;
+	if (msg.rx.ret)
+		return -EINVAL;
+
+	return 0;
 }
 
 static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie,
@@ -1254,6 +1261,7 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie,
 	struct mrq_uphy_response resp;
 	struct tegra_bpmp_message msg;
 	struct mrq_uphy_request req;
+	int err;
 
 	memset(&req, 0, sizeof(req));
 	memset(&resp, 0, sizeof(resp));
@@ -1273,7 +1281,13 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie,
 	msg.rx.data = &resp;
 	msg.rx.size = sizeof(resp);
 
-	return tegra_bpmp_transfer(pcie->bpmp, &msg);
+	err = tegra_bpmp_transfer(pcie->bpmp, &msg);
+	if (err)
+		return err;
+	if (msg.rx.ret)
+		return -EINVAL;
+
+	return 0;
 }
 
 static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie)
-- 
2.51.0