Re: [PATCH] drm/msm/a6xx: fix bogus hwcg register updates

[Johan Hovold <johan@kernel.org>]

On Sun, Dec 21, 2025 at 05:45:52PM +0100, Johan Hovold wrote:
> The hw clock gating register sequence consists of register value pairs
> that are written to the GPU during initialisation.
> 
> The a690 hwcg sequence has two GMU registers in it that used to amount
> to random writes in the GPU mapping, but since commit 188db3d7fe66
> ("drm/msm/a6xx: Rebase GMU register offsets") they trigger a fault as
> the updated offsets now lie outside the mapping. This in turn breaks
> boot of machines like the Lenovo ThinkPad X13s.
> 
> Note that the updates of these GMU registers is already taken care of
> properly since commit 40c297eb245b ("drm/msm/a6xx: Set GMU CGC
> properties on a6xx too"), but for some reason these two entries were
> left in the table.
> 
> Fixes: 5e7665b5e484 ("drm/msm/adreno: Add Adreno A690 support")
> Cc: stable@vger.kernel.org	# 6.5
> Cc: Bjorn Andersson <andersson@kernel.org>
> Cc: Konrad Dybcio <konradybcio@kernel.org>
> Signed-off-by: Johan Hovold <johan@kernel.org>
> ---

This one does not seem to have been applied yet despite fixing a
critical regression in 6.19-rc1. I guess I could have highlighted that
further by also including:

Fixes: 188db3d7fe66 ("drm/msm/a6xx: Rebase GMU register offsets")

I realise some delays are expected around Christmas, but can you please
try to get this fix to Linus now that everyone should be back again?

Johan