From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A4EB308F33; Thu, 22 Jan 2026 09:41:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769074869; cv=none; b=OBsxtril8gFuFhMfTsao4f/R1+qTN5VZD+Qi0H9uOhcIpetbH0ZN3nDnwJuaswDpocigl4FkS9D/UkLQrSFH95RFMFmqtHQUoWvXwNd0gzY7vnAeZEdzvLeDYqC/YMi3Z2/cNsOCB1/P1z0Pum7xkyz2PEGGab1E2QNK5ifAsl4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769074869; c=relaxed/simple; bh=ULYW/RP0yu7Z99OE1vPmkiwP012bx0rlTW+FCdIDYmc=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=FS6OhoSk3aMndcdEOhyRBR4nfX8XVhTRd+kgSUg0bDHzsHBrrWftsjlbkrhSCNXIr8CC5K6kHAHOKYeKBgif62P6yXTOwoBszq63oPngYOFwU+792Fu5Ix73tkMgy+VV3L4zoV1c6eDEQGbo/NUqgFRu97dfxjob1MAs1phY1SA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SIPtWEcK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SIPtWEcK" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 789EFC116C6; Thu, 22 Jan 2026 09:41:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769074867; bh=ULYW/RP0yu7Z99OE1vPmkiwP012bx0rlTW+FCdIDYmc=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=SIPtWEcKNGS0u07v7qFDECVGvCyv6rnxV6zPa5z35e5MkBSDph9xXnxhQEcOtZgWX Jh2L561z4a8Eb9zXxgdha2KZPD/bVH8bRD8YYQVICHZ35W/rGQCZv13UmQqN+Q2mJ0 +ZUJzyQPH8u7Sd0RkGIaY6w7zwXVTB9k77ChA0ciApSBDWnb/Y8g5C9kOM5ysua9TH fGrZLDTiXxAzczZnc8shj6Ig4r6ipMWehlkbVohJcjNBs6yS1h07XZG8VmWgPpZVQc +McUT7glVR8tz8o10wtWBm225RKY73eZMjI99lY3tMAWJ7m/C4xllU2OSlypEWZdVC nre+DhGxBEhug== Received: from johan by xi.lan with local (Exim 4.98.2) (envelope-from ) id 1virBW-000000003RU-2WW7; Thu, 22 Jan 2026 10:41:02 +0100 Date: Thu, 22 Jan 2026 10:41:02 +0100 From: Johan Hovold To: Rob Clark Cc: Sean Paul , Konrad Dybcio , Akhil P Oommen , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, David Airlie , Simona Vetter Subject: Re: [PATCH] drm/msm/a6xx: fix bogus hwcg register updates Message-ID: References: <20251221164552.19990-1-johan@kernel.org> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: [ +CC: Dave and Simona ] On Wed, Jan 21, 2026 at 08:59:51AM -0800, Rob Clark wrote: > On Wed, Jan 21, 2026 at 7:17 AM Johan Hovold wrote: > > > > On Wed, Jan 14, 2026 at 09:56:12AM +0100, Johan Hovold wrote: > > > On Sun, Dec 21, 2025 at 05:45:52PM +0100, Johan Hovold wrote: > > > > The hw clock gating register sequence consists of register value pairs > > > > that are written to the GPU during initialisation. > > > > > > > > The a690 hwcg sequence has two GMU registers in it that used to amount > > > > to random writes in the GPU mapping, but since commit 188db3d7fe66 > > > > ("drm/msm/a6xx: Rebase GMU register offsets") they trigger a fault as > > > > the updated offsets now lie outside the mapping. This in turn breaks > > > > boot of machines like the Lenovo ThinkPad X13s. > > > > > > > > Note that the updates of these GMU registers is already taken care of > > > > properly since commit 40c297eb245b ("drm/msm/a6xx: Set GMU CGC > > > > properties on a6xx too"), but for some reason these two entries were > > > > left in the table. > > > > > > > > Fixes: 5e7665b5e484 ("drm/msm/adreno: Add Adreno A690 support") > > > > Cc: stable@vger.kernel.org # 6.5 > > > > Cc: Bjorn Andersson > > > > Cc: Konrad Dybcio > > > > Signed-off-by: Johan Hovold > > > > --- > > > > > > This one does not seem to have been applied yet despite fixing a > > > critical regression in 6.19-rc1. I guess I could have highlighted that > > > further by also including: > > > > > > Fixes: 188db3d7fe66 ("drm/msm/a6xx: Rebase GMU register offsets") > > > > > > I realise some delays are expected around Christmas, but can you please > > > try to get this fix to Linus now that everyone should be back again? > > > > I haven't received any reply so was going to send another reminder, but > > I noticed now that this patch was merged to the msm-next branch last > > week. > > > > Since it fixes a regression in 6.19-rc1 it needs to go to Linus this > > cycle and I would have assumed it should have be merged to msm-fixes. > > > > (MSM) DRM works in mysterious ways, so can someone please confirm that > > this regression fix is heading into mainline for 6.19-final? > > Sorry, mesa 26.0 branchpoint this week so I've not had much time for > kernel for last few weeks and didn't have time for a 2nd msm-fixes PR. > But with fixes/cc tags it should be picked into 6.19.y I'm afraid that's not good enough as this is a *regression* breaking the display completely on machines like the X13s. Regression fixes should go to mainline this cycle since we don't knowingly break users' setups (and force them to debug/bisect when they update to 6.19 while the fix has been available since before Christmas). Can't you just send a PR with this single fix? Otherwise, perhaps Dave or Simona can pick up the fix directly? Johan