From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1FD120C461; Tue, 21 Apr 2026 22:29:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776810597; cv=none; b=UMs+YUitvhsSmr69Od8LcBG6lIPwZY7AgTyJPZKEJ3bVjPky8WGFDecJILi+rSpfrqVuJh9UMiN4Sr0szOWapfxSE7xBFjXVbKkGXx3Q5pBWIz4w9A2bb1/aaSWvBPoLlTSunLJMru2IGAWMM+EQmZdRAuQNs007urIawHdEgVw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776810597; c=relaxed/simple; bh=HwDAUHUeSrDiyXDXsV2CjHp8PEOM2HcnKUqP6U1hhkY=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=XIo7/J8RUihqLjCypejctV5AAycUIKpsPWwsJattIVqAkiezW1IOsinXsWx0FkUFfH2pM778jM11DMms7udLyYFETS5wDQeTlf2qiEfkFtLzT8vB0hD8DiZiWjzLjhyh1S7YS2y8tpF5B3vk6Ya3r3qS7oZafmJ4ngwG2YnmgUI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=aVj72BD8; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="aVj72BD8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776810596; x=1808346596; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=HwDAUHUeSrDiyXDXsV2CjHp8PEOM2HcnKUqP6U1hhkY=; b=aVj72BD8T3acQdbAXtk+nFa4zUVsW7LZi2iuNPcuaqZScczHADL+QGmi bAfK6H5nDZjSxNtLitoRW885tEH1u5QxkkYRkwQ4JG1pXHni9gjJA3Efl gGSaEQN1ark5bPud1UbI0sY/uYXu1BAqJz4slvFiR7WTZluCfutep73Kx L24uB9Q7tiyZoSLeVOTLcIxN3d9jDdUBNvBYWZp2DmQKbTMTVmTqkLn05 4bSdAPsnH8u/LIiv/OPX8rswWsQ4PDJPP6/VQfEnWkVuAF5/Dq6ndnRaF qGaUQbjhh2Zi3vapqGbq0Sn7tgM20Z3FTHICG9bwYGJ4mb+bL9i6nlLJm g==; X-CSE-ConnectionGUID: ycB7Nxx7TM2y7pxAz1+Keg== X-CSE-MsgGUID: NwkAQk6OSpm3VIN221NQGg== X-IronPort-AV: E=McAfee;i="6800,10657,11763"; a="77460346" X-IronPort-AV: E=Sophos;i="6.23,192,1770624000"; d="scan'208";a="77460346" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2026 15:29:55 -0700 X-CSE-ConnectionGUID: mN3c3u+XSLOHLQmiklDPOw== X-CSE-MsgGUID: bUyq77UxTKGum+t66b0wiQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,192,1770624000"; d="scan'208";a="227553036" Received: from tassilo.jf.intel.com (HELO tassilo) ([10.54.38.190]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2026 15:29:54 -0700 Date: Tue, 21 Apr 2026 15:29:50 -0700 From: Andi Kleen To: Dapeng Mi Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Eranian Stephane , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , stable@vger.kernel.org Subject: Re: [Patch v2 1/4] perf/x86/intel: Clear stale ACR mask before updating new mask Message-ID: References: <20260420024528.2130065-1-dapeng1.mi@linux.intel.com> <20260420024528.2130065-2-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260420024528.2130065-2-dapeng1.mi@linux.intel.com> > diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c > index 4768236c054b..774ae9a4eeaf 100644 > --- a/arch/x86/events/intel/core.c > +++ b/arch/x86/events/intel/core.c > @@ -3334,6 +3334,12 @@ static void intel_pmu_acr_late_setup(struct cpu_hw_events *cpuc) > struct perf_event *event, *leader; > int i, j, idx; > > + /* Clear stale ACR mask first. */ > + for (i = 0; i < cpuc->n_events; i++) { > + event = cpuc->event_list[i]; > + event->hw.config1 = 0; > + } Are you sure nothing else could be using config1? In principle ACR events can be used with some config1 setting. -Andi