From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84C9131282F; Tue, 21 Apr 2026 22:37:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776811047; cv=none; b=WLmJDOL90bv0k6w8F4FO76AIwY49tHpPxzvKEO+SabDgXFqiBLYbYCro6boaRIxl73ZwgnWVhd+ig3lq9cdn8cPsQM9Gv6/DF+AOnswXSaAwmpebJd70RgiBiw5bMAekC6evyFVPSy6Xj2Ykb5KQixOrcHdInlooHp+SEdrujPM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776811047; c=relaxed/simple; bh=9asddOYunBnLRNQiRd5AYd47HrnxvGGkWFIRCnjNamY=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=r4FUVR9GMeftolxSnswvOTtrCk70AfX71MHcMQdarv/zY710z1yKT7GKtNtNTDcf5KE7Pn7ItcJGSF8+UWjRXcUvNW4mu5IvKduRE+lrMiHPav81cEuMIQ6GvzlcnJ2AiZiWVQH9Kc1KNVHyEkBUVgDEJPH1p9McfwdnZuWtcVo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=WaXyqS3k; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WaXyqS3k" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776811046; x=1808347046; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=9asddOYunBnLRNQiRd5AYd47HrnxvGGkWFIRCnjNamY=; b=WaXyqS3knDUZqfJHEIWALQdWTOdjlaj5wub5G0exDtD37I2/grY1VTa4 1lj71r7Zz4QRHG/IJsKLCkcstNP1UwqyXKwOtLh5SNR1FVWHlKNmlfy9c y+R6RIbTvwdZQcx7+Mek3nfNXp1KEqYipWfvBp26r161ral9jBRtnfvOd qvnEfnD0VDh4ULyk3QwkO414s/F01BbupoF/xx4x5xg/2Nb6d9e1ofRzH k5uP3FURWnUXQlbR+aQUgnjn7lOO0SP/5YGfs7ODacpMNooqermxnPFGt ePAQ6j9Y6yYBZTepAupEBRR2CqbOmKcWknEaMg0iVr3re8+tU+IrkI2Cs w==; X-CSE-ConnectionGUID: Pu7bgGWdRB292F8NepyWow== X-CSE-MsgGUID: I3+QqWRnQZWdG2RX3ngGng== X-IronPort-AV: E=McAfee;i="6800,10657,11763"; a="77670599" X-IronPort-AV: E=Sophos;i="6.23,192,1770624000"; d="scan'208";a="77670599" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2026 15:37:25 -0700 X-CSE-ConnectionGUID: LV++u1zaSXm15/wOZgckRw== X-CSE-MsgGUID: ueANhsdgQh+/0shTyaXZKQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,192,1770624000"; d="scan'208";a="262567024" Received: from tassilo.jf.intel.com (HELO tassilo) ([10.54.38.190]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2026 15:37:25 -0700 Date: Tue, 21 Apr 2026 15:37:22 -0700 From: Andi Kleen To: Dapeng Mi Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Eranian Stephane , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , stable@vger.kernel.org Subject: Re: [Patch v2 2/4] perf/x86/intel: Disable PMI for self-reloaded ACR events Message-ID: References: <20260420024528.2130065-1-dapeng1.mi@linux.intel.com> <20260420024528.2130065-3-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260420024528.2130065-3-dapeng1.mi@linux.intel.com> On Mon, Apr 20, 2026 at 10:45:26AM +0800, Dapeng Mi wrote: > @@ -3306,6 +3306,15 @@ static void intel_pmu_enable_event(struct perf_event *event) > intel_set_masks(event, idx); > static_call_cond(intel_pmu_enable_acr_event)(event); > static_call_cond(intel_pmu_enable_event_ext)(event); > + /* > + * For self-reloaded ACR event, don't enable PMI since > + * HW won't set overflow bit in GLOBAL_STATUS. Otherwise, > + * the PMI would be recognized as a suspicious NMI. > + */ > + if (is_acr_self_reload_event(event)) > + hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT; > + else if (!event->attr.precise_ip) > + hwc->config |= ARCH_PERFMON_EVENTSEL_INT; It seems weird to either clear or set the bit. You don't know the previous state of the bit here? I would assume it starts with zero? > +static inline bool is_acr_self_reload_event(struct perf_event *event) > +{ > + struct hw_perf_event *hwc = &event->hw; > + > + if (hwc->idx < 0) > + return false; > + > + return test_bit(hwc->idx, (unsigned long *)&hwc->config1); Are you sure this doesn't conflict with some other non ACR usage of config1? -Andi